With Bachelor's in Computer Engineering, I'm Having a high passion for a wide-range understanding of complex systems/solutions from the very high level of OSes and Architecture down to the very low level of IC design and FPGA. I’m actively seeking challenging projects in digital hardware Design/Verification where my skills, work experience, and academic background can significantly both contribute to future technologies enablement and be developed Skills: Working on RTLs written in both VHDL and Verilog Knowledgeable of Design Methodologies like Power-Aware Design, CDC & DFT. Knowledgeable of Back-End flow like Clock Tree Synthesis, Placement & Routing. Knowledgeable of Verification Methodologies Both UVM & System Verilog. Scripting using: TCL. Design and Simulation Tools: Modelsim - Xilinx ISE Design Suite- Intel Quartus prime- Cadence Virtuoso- Synopsys Design Compiler- Cadence SOC Encounter.