Skip to content

Commit

Permalink
cleanup
Browse files Browse the repository at this point in the history
  • Loading branch information
yhx committed Jun 7, 2016
1 parent 2e800e5 commit 5b49941
Show file tree
Hide file tree
Showing 17 changed files with 15 additions and 310 deletions.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
188 changes: 0 additions & 188 deletions RTL/ll_ccie/cycle_detection_pe.v

This file was deleted.

104 changes: 0 additions & 104 deletions RTL/ll_ccie/fifo.v

This file was deleted.

29 changes: 13 additions & 16 deletions RTL/ll_ccie/matrix_multiply_buf_pl.v
Original file line number Diff line number Diff line change
Expand Up @@ -78,35 +78,32 @@ module matrix_multiply_buf_pl #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DA

reg [3:0] r_state, n_state;

wire run, accu_run;
wire run;
assign run = (r_state == STATE_RUN) && (!r_done);
assign accu_run = (r_state == STATE_ADDUP) && (!r_done);

//Perf manage
reg [DATA_WIDTH-1:0] perf_cnt;
reg [DATA_WIDTH-1:0] perf_start;

// Base address
reg [ADDR_LMT-1:0] addr_vec2;
reg [ADDR_LMT-1:0] addr_wr_base;
wire [ADDR_LMT-1:0] addr_vec2;
wire [ADDR_LMT-1:0] addr_wr_base;


// INIT parameter
reg [CACHE_WIDTH-1:0] para, n_para;

wire [DATA_WIDTH-1:0] M;
wire [DATA_WIDTH-1:0] N;
wire [DATA_WIDTH-1:0] P;
wire [DATA_WIDTH-1:0] MN;
wire [DATA_WIDTH-1:0] MP;
wire [DATA_WIDTH-1:0] PN;
wire [DATA_WIDTH-1:0] BN;
assign M = para[31:0];
assign N = para[63:32];
assign P = para[95:64];
wire [ADDR_LMT-1:0] M;
wire [ADDR_LMT-1:0] N;
wire [ADDR_LMT-1:0] P;
wire [ADDR_LMT-1:0] MN;
wire [ADDR_LMT-1:0] MP;
wire [ADDR_LMT-1:0] PN;
assign M = para[ADDR_LMT-1:0];
assign N = para[DATA_WIDTH + ADDR_LMT-1:DATA_WIDTH];
assign P = para[DATA_WIDTH + DATA_WIDTH + ADDR_LMT-1: DATA_WIDTH+DATA_WIDTH];
assign MN = M * N;
assign PN = P * N;
assign BN = RAM_DEPTH/N;
assign MP = M * P;
assign addr_vec2 = addr_vec1 + MN;
assign addr_wr_base = ((MN + PN + 1)<<4);
Expand Down Expand Up @@ -152,7 +149,7 @@ module matrix_multiply_buf_pl #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DA
accuer (
.clk (clk),
.rst (rst),
.size_out (N),
.size_out ({12'd0, N}),
.inc (ready_mul),
.array (res_mul),
.res (res_accu),
Expand Down
2 changes: 1 addition & 1 deletion RTL/ll_ccie/write_buffer_pl.v
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ module write_buffer_pl #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDT

buffer[index_addr +: 32] <= wr_en ? wr_data[31:0] : buffer[index_addr +: 32];
cur_addr <= wr_en ? cl_addr : cur_addr;
buf_mdata <= wr_en ? wr_mdata : 'd0;
buf_mdata <= wr_en ? wr_mdata : 14'd0;

if (wr_real)
begin
Expand Down
Binary file modified SW/matrix_mul
Binary file not shown.
2 changes: 1 addition & 1 deletion SW/matrix_mul.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -438,7 +438,7 @@ int matrixMulApp::run()
int *ptr = (int*)pSource;
//INIT
FILE *f = NULL;
const int M = 240, N = 15, P = 5;
const int M = 24, N = 2, P = 15;
const int M_ = ((M+15)>>4)<<4;
ptr[0] = M;
ptr[1] = N;
Expand Down

0 comments on commit 5b49941

Please sign in to comment.