FULL MATRIX MUL

yhx · May 31, 2016 · 4142dbc · 4142dbc
1 parent e7dd678
commit 4142dbc
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Showing 10 changed files with 635 additions and 153 deletions.
diff --git a/RTL/ll_ccie/afu_core.v b/RTL/ll_ccie/afu_core.v
@@ -279,7 +279,9 @@ module afu_core #(MDATA = 14)
               // afu_user not done, handle its wr_req
               if (!uafu_done) begin
                  cor_tx_wr_valid <= uafu_wr_req_en;
-                 cor_tx_wr_addr  <= ctx_dst_ptr + uafu_wr_req_addr;
+                 // TODO: Write to and read from different address.
+		 //cor_tx_wr_addr  <= ctx_dst_ptr + uafu_wr_req_addr;
+                 cor_tx_wr_addr  <= ctx_src_ptr + uafu_wr_req_addr;
                  cor_tx_wr_data  <= uafu_wr_req_data;
                  cor_tx_wr_mdata <= uafu_wr_req_mdata;
               end else begin

diff --git a/RTL/ll_ccie/afu_user_wb.v b/RTL/ll_ccie/afu_user_wb.v
@@ -40,11 +40,13 @@ module afu_user_wb #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDTH =
 
 	/* buf write port */
 	wire [ADDR_LMT+3:0] wb_req_addr;
-	wire [31:0]	wb_req_data;
+	wire [CACHE_WIDTH-1:0]	wb_req_data;
 	wire [MDATA-1:0]	wb_req_mdata;
 	wire 		wb_req_en;
 	wire 	        wb_req_now;
+	wire 	        wb_req_direct;
 	wire 	        wb_rsp_valid;
+	wire 	        wb_rsp_rvalid;
 
 	wire 		user_clk;
 
@@ -83,14 +85,16 @@ module afu_user_wb #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDTH =
 		.wr_data		(wb_req_data),
 		.wr_mdata		(wb_req_mdata),
 		.wr_en			(wb_req_en),
+		.wr_direct		(wb_req_direct),
 
 		.wr_valid		(wb_rsp_valid), 
+		.wr_real_valid		(wb_rsp_rvalid), 
 
 		.start 			(start)
 	);
 
-	matrix_multiply #(
-	//matrix_multiply_pl #(
+	//matrix_multiply #(
+	matrix_multiply_pl #(
 		.ADDR_LMT(ADDR_LMT),
 		.MDATA(MDATA), 
 		.CACHE_WIDTH(CACHE_WIDTH),
@@ -117,11 +121,13 @@ module afu_user_wb #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDTH =
 		.wr_req_data       	(wb_req_data),
 		.wr_req_en         	(wb_req_en),
 		.wr_req_now         	(wb_req_now),
+		.wr_req_direct         	(wb_req_direct),
 		.wr_req_almostfull 	(wr_req_almostfull),
 
 
 		// wr rsp 
 		.wr_rsp_valid     	(wb_rsp_valid),
+		.wr_rsp_rvalid     	(wb_rsp_rvalid),
 
 		// ctrl 
 		.start			(start),

diff --git a/RTL/ll_ccie/array_accu_pl.v b/RTL/ll_ccie/array_accu_pl.v
@@ -0,0 +1,48 @@
+module array_accu_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
+	(
+		input clk,
+		input rst,
+		input inc,
+		input [CACHE_WIDTH-1:0] array,
+		output [CACHE_WIDTH-1:0] res,
+		output ready
+	);
+
+	localparam DATA_SIZE = CACHE_WIDTH/DATA_WIDTH;
+
+	reg [CACHE_WIDTH-1:0] add_0_res;
+
+	assign res = add_0_res;
+
+	reg enable0;
+	assign ready = enable0 && !inc;
+
+	always@(posedge clk)
+	begin
+		enable0 <= rst ? 1'b0 : inc;
+	end
+
+	genvar i;
+	generate for (i=0; i<DATA_SIZE; i++)
+		begin:adder
+			always@(posedge clk)
+			begin
+				if (rst)
+				begin
+					add_0_res <= 0;
+				end
+				else if (inc)
+				begin
+					add_0_res[i<<5 +: DATA_WIDTH] <= array[i<<5 +: DATA_WIDTH] + add_0_res[i<<5 +: DATA_WIDTH];
+				end
+				else
+				begin
+					//$display("ADD_RES: %d@%d, %d@%d", add_3_res[0], 0, add_3_res[1], 1);
+					add_0_res[i<<5 +: DATA_WIDTH] <= array[i<<5 +: DATA_WIDTH];
+				end
+			end
+		end
+	endgenerate
+
+endmodule
+
diff --git a/RTL/ll_ccie/array_add_pl.v b/RTL/ll_ccie/array_add_pl.v
@@ -0,0 +1,46 @@
+module array_add_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
+	(
+		input clk,
+		input rst,
+		input enable,
+		input [CACHE_WIDTH-1:0] array1,
+		input [CACHE_WIDTH-1:0] array2,
+		output [CACHE_WIDTH-1:0] res,
+		output ready
+	);
+
+	localparam DATA_SIZE = CACHE_WIDTH/DATA_WIDTH;
+
+	reg [DATA_WIDTH-1:0] add_0_res;
+
+	assign res = add_0_res;
+
+	reg enable0;
+	assign ready = enable0;
+
+	always@(posedge clk)
+	begin
+		enable0 <= rst ? 1'b0 : enable;
+	end
+
+	genvar i;
+	generate for (i=0; i<DATA_SIZE; i++)
+		begin:adder
+			always@(posedge clk)
+			begin
+				if (enable)
+				begin
+					//$display("ADD_RES: %d@%d, %d@%d", add_3_res[0], 0, add_3_res[1], 1);
+					add_0_res[i<<5 +: DATA_WIDTH] <= array1[i<<5 +: DATA_WIDTH] + array1[i<<5 +: DATA_WIDTH];
+
+				end
+				else 
+				begin
+					add_0_res[i<<5 +: DATA_WIDTH] <= 'd0;
+				end
+			end
+		end
+	endgenerate
+
+endmodule
+
diff --git a/RTL/ll_ccie/array_mul_pl.v b/RTL/ll_ccie/array_mul_pl.v
@@ -30,11 +30,11 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
 
 	always@(posedge clk)
 	begin
-		enable1 <= rst ? 1'd0 : enable;
-		enable2 <= rst ? 1'd0 : enable1;
-		enable3 <= rst ? 1'd0 : enable2;
-		enable4 <= rst ? 1'd0 : enable3;
-		enable0 <= rst ? 1'd0 : enable4;
+		enable1 <= rst ? 1'b0 : enable;
+		enable2 <= rst ? 1'b0 : enable1;
+		enable3 <= rst ? 1'b0 : enable2;
+		enable4 <= rst ? 1'b0 : enable3;
+		enable0 <= rst ? 1'b0 : enable4;
 	end
 
 	//multiplier size 16
@@ -45,7 +45,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
 			begin
 				if (enable && (!rst))
 				begin
-					$display("ARRAY1: %d, ARRAY2: %d", array1[i*DATA_WIDTH +: DATA_WIDTH], array2[i*DATA_WIDTH +: DATA_WIDTH]);
+					//$display("ARRAY1: %d, ARRAY2: %d", array1[i*DATA_WIDTH +: DATA_WIDTH], array2[i*DATA_WIDTH +: DATA_WIDTH]);
 					mul_res[i] <= array1[i*DATA_WIDTH +: DATA_WIDTH] * array2[i*DATA_WIDTH +: DATA_WIDTH];
 				end
 				else 
@@ -64,7 +64,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
 			begin
 				if (enable1)
 				begin
-					$display("MUL_RES: %d, %d", mul_res[j*2], mul_res[j*2+1]);
+					//$display("MUL_RES: %d, %d", mul_res[j*2], mul_res[j*2+1]);
 					add_1_res[j] <= mul_res[j*2] + mul_res[j*2 + 1];
 				end
 				else
@@ -83,7 +83,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
 			begin
 				if (enable2)
 				begin
-					$display("ADD_1_RES: %d, %d", add_1_res[k*2], add_1_res[k*2+1]);
+					//$display("ADD_1_RES: %d, %d", add_1_res[k*2], add_1_res[k*2+1]);
 					add_2_res[k] <= add_1_res[k*2] + add_1_res[k*2 + 1];
 				end
 				else
@@ -102,7 +102,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
 			begin
 				if (enable3)
 				begin
-					$display("ADD_2_RES: %d, %d", add_2_res[l*2], add_1_res[l*2+1]);
+					//$display("ADD_2_RES: %d, %d", add_2_res[l*2], add_1_res[l*2+1]);
 					add_3_res[l] <= add_2_res[l*2] + add_2_res[l*2 + 1];
 				end
 				else
@@ -117,7 +117,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
 	begin
 		if (enable4)
 		begin
-			$display("ADD_3_RES: %d@%d, %d@%d", add_3_res[0], 0, add_3_res[1], 1);
+			//$display("ADD_3_RES: %d@%d, %d@%d", add_3_res[0], 0, add_3_res[1], 1);
 			add_0_res <= add_3_res[0] + add_3_res[1];
 		end
 		else