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newer write_buf
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@yhx
yhx committed Jun 6, 2016
1 parent 4142dbc commit 0ea5b09
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Showing 14 changed files with 1,012 additions and 140 deletions.
1 change: 1 addition & 0 deletions .gitignore
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*.bak
*.o
*.log
*.txt
106 changes: 106 additions & 0 deletions RTL/ll_ccie/afu_user_test.v
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@@ -0,0 +1,106 @@
module afu_user_test #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512)
(
input clk,
input reset_n,

// Read Request
output [ADDR_LMT-1:0] rd_req_addr,
output [MDATA-1:0] rd_req_mdata,
output rd_req_en,
input rd_req_almostfull,

// Read Response
input rd_rsp_valid,
input [MDATA-1:0] rd_rsp_mdata,
input [CACHE_WIDTH-1:0] rd_rsp_data,

// Write Request
output [ADDR_LMT-1:0] wr_req_addr,
output [MDATA-1:0] wr_req_mdata,
output [CACHE_WIDTH-1:0] wr_req_data,
output wr_req_en,
input wr_req_almostfull,

// Write Response
input wr_rsp0_valid,
input [MDATA-1:0] wr_rsp0_mdata,
input wr_rsp1_valid,
input [MDATA-1:0] wr_rsp1_mdata,

// Start input signal
input start,

// Done output signal
output done

// Control info from software
//input [511:0] afu_context
);
/* DBS's favorite polarity */
wire rst = ~reset_n;

localparam addr_vec1 = 'd1;

/* read port */
reg [ADDR_LMT-1:0] r_rd_req_addr;
reg [MDATA-1:0] r_rd_req_mdata;
reg r_rd_req_en;
assign rd_req_addr = r_rd_req_addr;
assign rd_req_mdata = r_rd_req_mdata;
assign rd_req_en = r_rd_req_en;

/* write port */
reg [ADDR_LMT-1:0] r_wr_req_addr;
reg [MDATA-1:0] r_wr_req_mdata;
reg r_wr_req_en;
reg [511:0] r_wr_req_data;
assign wr_req_addr = r_wr_req_addr;
assign wr_req_mdata = r_wr_req_mdata;
assign wr_req_en = r_wr_req_en;
assign wr_req_data = r_wr_req_data;

reg [4:0] r_state, n_state;
reg r_done,n_done;


assign run = !r_done;

reg [ADDR_LMT-1:0] vec1_idx;
reg rd_req_f;

assign done = rd_req_f;
always@(posedge clk)
begin
if (run && !rd_req_almostfull && !rd_req_f)
begin
r_rd_req_addr <= addr_vec1;
$display("Read Vec1: %d", addr_vec1);

r_rd_req_mdata <= 'd0;
r_rd_req_en <= 1'b1;

if (vec1_idx >= 540000)
begin
rd_req_f <= 1'b1;
end
else
begin
vec1_idx <= vec1_idx + 1;
end
end
else
begin
if (rst)
begin
rd_req_f <= 1'b0;

vec1_idx <= 'd0;
end

r_rd_req_addr <= 'd0;
r_rd_req_mdata <= 'd0;
r_rd_req_en <= 'd0;
end
end

endmodule
7 changes: 4 additions & 3 deletions RTL/ll_ccie/afu_user_wb.v
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Expand Up @@ -57,7 +57,8 @@ module afu_user_wb #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDTH =
// .clk_o (user_clk)
//);

write_buffer #(
//write_buffer #(
write_buffer_pl #(
.ADDR_LMT(ADDR_LMT),
.MDATA(MDATA),
.CACHE_WIDTH(CACHE_WIDTH),
Expand All @@ -66,6 +67,7 @@ module afu_user_wb #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDTH =
wbuf(
.clk (clk),
.rst (rst),
//.start (start),

.wr_req_addr (wr_req_addr),
.wr_req_mdata (wr_req_mdata),
Expand All @@ -88,9 +90,8 @@ module afu_user_wb #(ADDR_LMT = 20, MDATA = 14, CACHE_WIDTH = 512, DATA_WIDTH =
.wr_direct (wb_req_direct),

.wr_valid (wb_rsp_valid),
.wr_real_valid (wb_rsp_rvalid),
.wr_real_valid (wb_rsp_rvalid)

.start (start)
);

//matrix_multiply #(
Expand Down
25 changes: 16 additions & 9 deletions RTL/ll_ccie/array_accu_pl.v
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Expand Up @@ -2,6 +2,7 @@ module array_accu_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
(
input clk,
input rst,
input out,
input inc,
input [CACHE_WIDTH-1:0] array,
output [CACHE_WIDTH-1:0] res,
Expand All @@ -11,38 +12,44 @@ module array_accu_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
localparam DATA_SIZE = CACHE_WIDTH/DATA_WIDTH;

reg [CACHE_WIDTH-1:0] add_0_res;
reg [CACHE_WIDTH-1:0] add_o_res;

assign res = add_0_res;
assign res = add_o_res;

reg enable0;
assign ready = enable0 && !inc;
assign ready = enable0;

always@(posedge clk)
begin
enable0 <= rst ? 1'b0 : inc;
enable0 <= rst ? 1'b0 : out;
end

genvar i;
generate for (i=0; i<DATA_SIZE; i++)
generate for (i=0; i<DATA_SIZE; i=i+1)
begin:adder
always@(posedge clk)
begin
if (rst)
begin
add_0_res <= 0;
add_0_res[i<<5 +: DATA_WIDTH] <= 0;
end
else if (out)
begin
$display("EN:%d, INC:%d, OUT:%d, ADD_RES: %d", enable0, inc, out, array[i<<5 +: DATA_WIDTH] + add_0_res[i<<5 +: DATA_WIDTH]);
add_o_res[i<<5 +: DATA_WIDTH] <= array[i<<5 +: DATA_WIDTH] + add_0_res[i<<5 +: DATA_WIDTH];
add_0_res[i<<5 +: DATA_WIDTH] <= 'd0;
end
else if (inc)
begin
$display("EN:%d, INC:%d, OUT:%d, ADD_RES: %d", enable0, inc, out, array[i<<5 +: DATA_WIDTH] + add_0_res[i<<5 +: DATA_WIDTH]);
add_0_res[i<<5 +: DATA_WIDTH] <= array[i<<5 +: DATA_WIDTH] + add_0_res[i<<5 +: DATA_WIDTH];
end
else
else
begin
//$display("ADD_RES: %d@%d, %d@%d", add_3_res[0], 0, add_3_res[1], 1);
add_0_res[i<<5 +: DATA_WIDTH] <= array[i<<5 +: DATA_WIDTH];
add_0_res[i<<5 +: DATA_WIDTH] <= add_0_res[i<<5 +: DATA_WIDTH];
end
end
end
endgenerate

endmodule

2 changes: 1 addition & 1 deletion RTL/ll_ccie/array_add_pl.v
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Expand Up @@ -24,7 +24,7 @@ module array_add_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)
end

genvar i;
generate for (i=0; i<DATA_SIZE; i++)
generate for (i=0; i<DATA_SIZE; i=i+1)
begin:adder
always@(posedge clk)
begin
Expand Down
8 changes: 4 additions & 4 deletions RTL/ll_ccie/array_mul_pl.v
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)

//multiplier size 16
genvar i;
generate for(i=0; i<DATA_SIZE; i++)
generate for(i=0; i<DATA_SIZE; i=i+1)
begin:multiplier
always@(posedge clk)
begin
Expand All @@ -58,7 +58,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)

//adder_1 size 8
genvar j;
generate for (j=0; j<(DATA_SIZE>>1); j++)
generate for (j=0; j<(DATA_SIZE>>1); j=j+1)
begin:adder_1
always@(posedge clk)
begin
Expand All @@ -77,7 +77,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)

//adder_2 size 4
genvar k;
generate for (k=0; k<(DATA_SIZE>>2); k++)
generate for (k=0; k<(DATA_SIZE>>2); k=k+1)
begin:adder_2
always@(posedge clk)
begin
Expand All @@ -96,7 +96,7 @@ module array_mul_pl #(CACHE_WIDTH = 512, DATA_WIDTH = 32)

//adder_3 size 2
genvar l;
generate for (l=0; l<(DATA_SIZE>>3); l++)
generate for (l=0; l<(DATA_SIZE>>3); l=l+1)
begin:adder_3
always@(posedge clk)
begin
Expand Down
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