A High-performance Timing Analysis Tool for VLSI Systems
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
5 Day TCL begginer to advanced training workshop by VSD
A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)
TCL Script automating the frontend of ASIC design
An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.
CAD in NYCU
This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).
This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).
Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite
Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite
5-Day TCL begginer to advanced workshop by VSD
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