; --------------------------------------

; zasm: assemble "clock.s"

; date: 2020-04-03 10:39:56

; --------------------------------------

; #define serial_loading 1

#target ROM

#include "platform.inc"

;---- Oscillator frequencies (in Hz)

; * FSYS is the primary system oscillator which drives the CPU.

; * FCTC is a secondary oscillator external to the CTC which can

; be prescaled and is fed in to the TRG1 input.

; * FUART is the frequency fed into the SIO clock inputs for baud

; rate generation.

8D80: FSYS .equ 6000000

8000: FCTC .equ 4096000

8000: FUART .equ 7372800

;---- Memory sizes (in bytes)

; Define the start (base) and size of ROMs and RAM.

#if defined(serial_loading)

ROM_BASE .equ 0x6000

ROM_SZ .equ 6144

RAM_BASE .equ 0x7800

RAM_SZ .equ 1792

#else

0000: ROM_BASE .equ 0

6000: ROM_SZ .equ 24576

6000: RAM_BASE .equ 0x6000

2000: RAM_SZ .equ 8192

#endif

C000: TZ_ROM_BASE .equ 0xC000

2000: TZ_ROM_SZ .equ 8192

E000: CHAR_ROM_BASE .equ 0xE000

2000: CHAR_ROM_SZ .equ 8192

;---- Vector interrupt page number

; Forms the most significant byte of the interrupt vector address

; for Mode 2 interrupts.

0001: VECTOR_INT_PG .equ (ROM_BASE+0x100)>>8

; END platform.inc

#include "ctc.inc"

0001: CTC_CTL_WORD .equ 0x1 ; This is a control word

0002: CTC_CTL_SW_RESET .equ 0x2 ; Perform SW reset on channel

0004: CTC_CTL_TCONST .equ 0x4 ; Time constant follows

0008: CTC_CTL_CLKTRG_ST .equ 0x8 ; CLK/TRG pulse starts timer

0010: CTC_CTL_RISE .equ 0x10 ; CLK/TRG rising edge

0020: CTC_CTL_PS_256 .equ 0x20 ; Prescaler of 256

0040: CTC_CTL_CTR_MODE .equ 0x40 ; Channel in counter mode

0080: CTC_CTL_INT_EN .equ 0x80 ; Enable interrupt on this channel

; END ctc.inc

#include "rtc.inc"

0040: RTC_ALM_ALM0 .equ 0x40

0080: RTC_ALM_ALM1 .equ 0x80

0000: RTC_RS_NONE .equ 0

0010: RTC_RS_30_5175US .equ 0x01 << 4

0020: RTC_RS_61_035US .equ 0x02 << 4

0030: RTC_RS_122_070US .equ 0x03 << 4

0040: RTC_RS_244_141US .equ 0x04 << 4

0050: RTC_RS_488_281US .equ 0x05 << 4

0060: RTC_RS_976_5625US .equ 0x06 << 4

0070: RTC_RS_1_95315MS .equ 0x07 << 4

0080: RTC_RS_3_90625MS .equ 0x08 << 4

0090: RTC_RS_7_8125MS .equ 0x09 << 4

00A0: RTC_RS_15_625MS .equ 0x0A << 4

00B0: RTC_RS_31_25MS .equ 0x0B << 4

00C0: RTC_RS_62_5MS .equ 0x0C << 4

00D0: RTC_RS_125MS .equ 0x0D << 4

00E0: RTC_RS_250MS .equ 0x0E << 4

00F0: RTC_RS_500MS .equ 0x0F << 4

0000: RTC_WD_1_5SEC .equ 0

0010: RTC_WD_23_4375MS .equ 0x01 << 4

0020: RTC_WD_46_875MS .equ 0x02 << 4

0030: RTC_WD_93_75MS .equ 0x03 << 4

0040: RTC_WD_187_5MS .equ 0x04 << 4

0050: RTC_WD_375MS .equ 0x05 << 4

0060: RTC_WD_750MS .equ 0x06 << 4

0070: RTC_WD_3S .equ 0x07 << 4

0001: RTC_INT_ABE .equ 0x01

0002: RTC_INT_PWRIE .equ 0x02

0004: RTC_INT_PIE .equ 0x04

0008: RTC_INT_AIE .equ 0x08

0001: RTC_FLAG_BVF .equ 0x01

0002: RTC_FLAG_PWRF .equ 0x02

0004: RTC_FLAG_PF .equ 0x04

0008: RTC_FLAG_AF .equ 0x08

0001: RTC_CTRL_DSE .equ 0x01

0002: RTC_CTRL_24HR .equ 0x02

0004: RTC_CTRL_RUN_BAT .equ 0x04

0008: RTC_CTRL_UTI .equ 0x08

; END rtc.inc

#include "clock.inc"

;---------------------------------------------------------------------

; PERIPHERAL CONFIGURATION & IO PORTS :

;---------------------------------------------------------------------

; CTC channel addresses

0000: CTC_CH0 .equ 0

0001: CTC_CH1 .equ 0x01

0002: CTC_CH2 .equ 0x02

0003: CTC_CH3 .equ 0x03

; CTC channel configuration

0001: CTC_CH0_CFG .equ CTC_CTL_WORD

00A5: CTC_CH1_CFG .equ CTC_CTL_INT_EN | CTC_CTL_PS_256 | CTC_CTL_TCONST | CTC_CTL_WORD

00A5: CTC_CH2_CFG .equ CTC_CTL_INT_EN | CTC_CTL_PS_256 | CTC_CTL_TCONST | CTC_CTL_WORD

00C5: CTC_CH3_CFG .equ CTC_CTL_INT_EN | CTC_CTL_CTR_MODE | CTC_CTL_TCONST | CTC_CTL_WORD

0017: CTC_CH1_TCONST .equ FSYS / 256 / 1000

00EA: CTC_CH2_TCONST .equ FSYS / 256 / 100

0001: CTC_CH3_TCONST .equ 0x01

; Watchdog poke register

0004: WDT_POKE .equ 0x04

; Buttons and switches

0008: BTN_REG .equ 0x08 ; Buttons/switches

; Masks

0001: BTN_UP .equ 0x01 ; Up button

0002: BTN_DN .equ 0x02 ; Down button

0004: BTN_ENT .equ 0x04 ; Enter button

0008: BTN_ESC .equ 0x08 ; Escape button

000F: BTN_ALL .equ 0x0F ; All buttons

0030: DIMM_ROW .equ 0x30 ; Dimming row bits

0040: DUTY_CYCLE .equ 0x40 ; Dimming duty cycle

; Bits

0000: BTN_UP_BIT .equ 0 ; Up button

0001: BTN_DN_BIT .equ 1 ; Down button

0002: BTN_ENT_BIT .equ 2 ; Enter button

0003: BTN_ESC_BIT .equ 3 ; Escape button

0004: DIMM_ROW_SW0 .equ 4 ; Dimming row select bit 0

0004: DIMM_ROW_SW1 .equ 4 ; Dimming row select bit 1

0006: DUTY_CYCLE_BIT .equ 6 ; Dimming duty cycle

0009: TZ_SW1_REG .equ 0x09 ; Switches 1 (timezone 1)

000A: TZ_SW2_REG .equ 0x0A ; Switches 2 (timezone 2)

000B: TZ_SW3_REG .equ 0x0B ; Switches 3 (timezone 3)

000C: OUTPUT_REG .equ 0x0C ; Outputs, e.g. beeper

; RTC register addresses

0010: RTC_SEC .equ 0x10

0011: RTC_SEC_ALM .equ 0x11

0012: RTC_MIN .equ 0x12

0013: RTC_MIN_ALM .equ 0x13

0014: RTC_HRS .equ 0x14

0015: RTC_HRS_ALM .equ 0x15

0016: RTC_DAY .equ 0x16

0017: RTC_DAY_ALM .equ 0x17

0018: RTC_DOW .equ 0x18

0019: RTC_MON .equ 0x19

001A: RTC_YEAR .equ 0x1A

001B: RTC_RATES .equ 0x1B

001C: RTC_INTS .equ 0x1C

001D: RTC_FLAGS .equ 0x1D

001E: RTC_CTRL .equ 0x1E

00C0: RTC_ALM_CFG .equ RTC_ALM_ALM1 | RTC_ALM_ALM0

0000: RTC_RATES_CFG .equ RTC_WD_1_5SEC | RTC_RS_NONE

0008: RTC_INTS_CFG .equ RTC_INT_AIE

0006: RTC_CTRL_CFG .equ RTC_CTRL_RUN_BAT | RTC_CTRL_24HR

; Display registers

0020: DISP_DATA .equ 0x20 ; Display data register

0021: DISP_CTRL .equ 0x21 ; Display control register

;---------------------------------------------------------------------

; TASK/APP CONSTANTS :

;---------------------------------------------------------------------

; Apps differ from tasks in that tasks can be (de)scheduled, while

; apps are scheduled at boot and dont become descheduled. They share

; common infrastructure, however.

0001: TASK_BUTTON_RD .equ 1 ; Button reader

0002: TASK_WD_POKE .equ 2 ; Poke the watchdog

0003: APP_CLOCK .equ 3 ; Clock application

0004: APP_CONFIGR .equ 4 ; Configuration application

0005: TASK_DISPLAY .equ 5 ; Display updater

;---------------------------------------------------------------------

; MISCELLANEOUS :

;---------------------------------------------------------------------

00DE: DEBUG_PORT .equ 0xDE

;---------------------------------------------------------------------

; MACROS :

;---------------------------------------------------------------------

;---------------------------------------------------------------------

; schedule_task :

; :

; Description :

; Schedule a task to be run at the next iteration of the main :

; loop. :

; :

; This is achieved by loading a positive value (the task number :

; itself, which is used as an offset) into the task's scheduling :

; byte. :

; :

; Parameters :

; task_num Task number to schedule :

; :

;---------------------------------------------------------------------

schedule_task .macro task_num

push HL

ld HL, task_sched+&task_num

ld (HL), &task_num

pop HL

.endm

;---------------------------------------------------------------------

; deschedule_task :

; :

; Description :

; De-schedule a task to prevent it from running during future :

; iterations of the main loop. :

; :

; This is achieved by loading a value of zero into the task's :

; scheduling byte. :

; :

; Parameters :

; task_num Task number to deschedule :

;---------------------------------------------------------------------

deschedule_task .macro task_num

push HL

ld HL, task_sched+&task_num

ld (HL), 0

pop HL

.endm

;---------------------------------------------------------------------

; run_task :

; :

; Description :

; Runs a task if it has been scheduled. :

; :

; A task is scheduled if its task scheduling byte contains any :

; non-zero value. :

; :

; Parameters :

; task_num Task number to run :

; call_label If scheduled, the label to CALL :

;---------------------------------------------------------------------

run_task .macro task_num, call_label

ld HL, task_sched+&task_num

ld A, (HL)

or A, A

call NZ, &call_label

.endm

;---------------------------------------------------------------------

; set_state :

; :

; Description :

; Update the value of a state machine variable. :

; :

; Parameters :

; sm Destination state machine variable :

; state State to be loaded :

;---------------------------------------------------------------------

set_state .macro sm, state

push AF

ld A, &state

ld (&sm), A

pop AF

.endm

;---------------------------------------------------------------------

; mtx_trylock :

; :

; Description :

; Attempts to acquire the mutex pointed to by the mutex :

; parameter. If the mutex cannot be immediately acquired :

; mtx_trylock will return 0, otherwise the mutex will be :

; acquired and a non-zero value will be returned. :

; :

; Interrupt safe: interrupts are disabled throughout the :

; critical code path, and restored to original :

; state upon completion. :

; :

; Parameters :

; mutex Address of mutex to acquire :

; task_num The task number that wants to acquire the mutex :

; :

; Returns :

; A 0 if lock not acquired, or task_num if acquired :

; F Z flag is set or cleared based on value of A :

;---------------------------------------------------------------------

mtx_trylock .macro mutex, task_num

push HL

ld A, I ; IFF2 to P/V flag

push AF ; Save flags

di ; Ensure interrupts disabled

ld HL, &mutex

ld A, (HL) ; Check current mutex owner

or A, A

jr Z, $+9 ; If zero, acquire it

cp A, &task_num ; If not zero, do we own it?

jr Z, $+8 ; Yes if Z, return mutex value

xor A, A ; No otherwise, return 0

jr $+5 ; Go to done

ld A, &task_num ; Acquire by loading task_num into

ld (HL), A ; mutex

pop HL ; F into L

bit 2, L ; Test IFF2 flag

jr Z, $+3 ; If IFF2 was not set, go to done

ei ; Re-enable interrupts

pop HL ; Done

or A, A ; Set Z flag according to A

.endm

;---------------------------------------------------------------------

; mtx_unlock :

; :

; Description :

; Releases a mutual exclusion lock. :

; :

; Interrupt safe: interrupts are disabled throughout the :

; critical code path, and restored to original :

; state upon completion. :

; :

; Parameters :

; mutex Address of mutex to unlock :

; :

; Returns :

; Nothing :

;---------------------------------------------------------------------

mtx_unlock .macro mutex

push AF

push HL

ld A, I ; IFF2 to P/V flag

push AF ; Save flags

di ; Ensure interrupts disabled

xor A, A ; Load zero to unlock the mutex

ld (&mutex), A

pop HL ; F into L

bit 2, L ; Test IFF2 flag

jr Z, $+3 ; If IFF2 was not set, go to done

ei ; Re-enable interrupts

pop HL ; Done

pop AF

.endm

;---------------------------------------------------------------------

; mtx_owned :

; :

; Description :

; Returns non-zero if the task indicated by the task_num param :

; owns the mutex. If that task does not hold the mutex, zero is :

; returned. :

; :

; Interrupt safe: interrupts are disabled throughout the :

; critical code path, and restored to original :

; state upon completion. :

; :

; Parameters :

; mutex Address of mutex to check ownership of :

; task_num The task number to compare :

; :

; Returns :

; A 0 if lock not owned, or task_num if owned :

; F Z flag is set or cleared based on value of A :

;---------------------------------------------------------------------

mtx_owned .macro mutex, task_num

push HL

ld A, I ; IFF2 to P/V flag

push AF ; Save flags

di ; Ensure interrupts disabled

ld A, (&mutex) ; Compare the value stored in

cp A, &task_num ; (mutex) with task_num.

jr Z, $+3

xor A, A ; Not equal, return 0

pop HL ; F into L

bit 2, L ; Test IFF2 flag

jr Z, $+3 ; If IFF2 was not set, go to done

ei ; Re-enable interrupts

pop HL ; Done

or A, A

.endm

;---------------------------------------------------------------------

; sem_post :

; :

; Description :

; Increment (unlock) a semaphore. :

; :

; Interrupt safe: interrupts are disabled throughout the :

; critical code path, and restored to original :

; state upon completion. :

; :

; Parameters :

; sem Address of semaphore to increment (unlock) :

; :

; Returns :

; Nothing :

;---------------------------------------------------------------------

sem_post .macro sem

push AF

push HL

ld A, I ; IFF2 to P/V flag

push AF ; Save flags

di ; Ensure interrupts disabled

ld HL, &sem

inc (HL)

pop HL ; F into L

bit 2, L ; Test IFF2 flag

jr Z, $+3 ; If IFF2 was not set, go to done

ei ; Re-enable interrupts

pop HL

pop AF

.endm

;---------------------------------------------------------------------

; sem_trywait :

; :

; Description :

; sem_trywait decrements (locks) the semaphore only if the value :

; is non-zero. Otherwise, the semaphore is not decremented and :

; an error (0) is returned. :

; :

; Interrupt safe: interrupts are disabled throughout the :

; critical code path, and restored to original :

; state upon completion. :

; :

; Parameters :

; sem Address of semaphore to increment (unlock) :

; :

; Returns :

; A 0 if semaphore locked, or semaphore value pre-decrement :

; F Z flag is set or cleared based on value of A :

;---------------------------------------------------------------------

sem_trywait .macro sem

push HL

ld A, I ; IFF2 to P/V flag

push AF ; Save flags

di ; Ensure interrupts disabled

ld HL, &sem

ld A, (HL) ; Load semaphore value for return

or A, A ; Semaphore value greater than 0?

jr Z, $+3 ; If Z, return 0, go to done

dec (HL) ; Decrement semaphore

pop HL ; F into L

bit 2, L ; Test IFF2 flag

jr Z, $+3 ; If IFF2 was not set, go to done

ei ; Re-enable interrupts

pop HL ; Done

or A, A ; Set Z flag according to A

.endm

;---------------------------------------------------------------------

; set_valid_btn_mask :

; :

; Description :

; Update the valid button mask to a new value. :

; :

; Presumably this is done while switching between states in an :

; app or task, so to prevent any unacknowledged or very recent :

; button presses being immediately acted upon within the new :

; state, those button presses are nulled out and made :

; acknowledged. Therefore the user will need to release those :

; button(s) before they can be re-recognised as new presses. :

; :

; Parameters :

; mask New button mask to apply :

; :

; Returns :

; Nothing :

;---------------------------------------------------------------------

set_valid_btn_mask .macro mask

push AF

push BC

ld A, (btn_state) ; Ack all un-ack'd buttons by

ld B, A ; OR'ing them with all ack'd

ld A, (btn_ack) ; buttons.

or A, B

ld (btn_ack), A

ld A, &mask

ld (btn_valid), A ; Load new mask

pop BC

pop AF

.endm

;---------------------------------------------------------------------

; ack_btn :

; :

; Description :

; Acknowledge a button press by setting its appropriate bit in :

; the btn_ack variable. :

;---------------------------------------------------------------------

ack_btn .macro button

push HL

ld HL, btn_ack ; Ack the button

set &button, (HL)

pop HL

.endm

;---------------------------------------------------------------------

; rtc_update_lock :

; :

; Description :

; Set the Update Transfer Inhibit bit of the RTC control :

; register. :

; :

; Prevents the RTC from updating public registers while they are :

; being read by an application. :

;---------------------------------------------------------------------

rtc_update_lock .macro

push AF

ld A, RTC_CTRL_UTI | RTC_CTRL_CFG

out (RTC_CTRL), A

pop AF

.endm

;---------------------------------------------------------------------

; rtc_update_unlock :

; :

; Description :

; Clear the Update Transfer Inhibit bit of the RTC control :

; register. :

; :

; Allows the RTC to update public registers so that their new :

; values may be read by an application. :

;---------------------------------------------------------------------

rtc_update_unlock .macro

push AF

ld A, RTC_CTRL_CFG

out (RTC_CTRL), A

pop AF

.endm

;---------------------------------------------------------------------

; get_jp_table_entry :

; :

; Description :

; Using A as an index, return the value of a double word from :

; the supplied table to be used as an address to perform a jump. :

; :

; The value of A is doubled and added to the supplied table :

; address. :

; :

; Parameters :

; table Address of the table to return entry from :

; :

; Returns :

; HL Address at index in jump table :

;---------------------------------------------------------------------

get_jp_table_entry .macro table

push DE

ld D, 0 ; DE becomes offset by doubling A

ld E, A

sla E

rl D

ld HL, &table ; HL = pointer to jump table

add HL, DE ; Add offset to pointer

ld E, (HL) ; Load HL pair into DE

inc HL

ld D, (HL)

ex DE, HL ; DE becomes HL for return

pop DE

.endm

; END clock.inc

6000: #data RAM, RAM_BASE, RAM_SZ-256

7F00: #data _INITIALIZED, *, 256

0000: #code ROM, ROM_BASE, ROM_SZ-256

5F00: #code _INITIALIZER, *, 256

#code ROM

;---------------------------------------------------------------------

; RESTART VECTORS :

;---------------------------------------------------------------------

.org ROM_BASE

0000: C30002 jp proc_test

0003: FFFFFFFF .org ROM_BASE+0x8 ; RST1

0007: FF

0008: 76 halt

0009: FFFFFFFF .org ROM_BASE+0x10 ; RST2

000D: FFFFFF

0010: 76 halt

0011: FFFFFFFF .org ROM_BASE+0x18 ; RST3

0015: FFFFFF

0018: 76 halt

0019: FFFFFFFF .org ROM_BASE+0x20 ; RST4

001D: FFFFFF

0020: 76 halt

0021: FFFFFFFF .org ROM_BASE+0x28 ; RST5

0025: FFFFFF

0028: 76 halt

0029: FFFFFFFF .org ROM_BASE+0x30 ; RST6

002D: FFFFFF

0030: 76 halt

0031: FFFFFFFF .org ROM_BASE+0x38 ; RST7

0035: FFFFFF

0038: 76 halt

;---------------------------------------------------------------------

; INTERRUPT VECTORS :

;---------------------------------------------------------------------

0039: FFFFFFFF .org ROM_BASE+0x66

003D: FF...

0066: nmi_vector

0066: 76 halt

0067: FFFFFFFF .org VECTOR_INT_PG<<8

006B: FF...

0100: int_vector_table

0100: 0013 .dw ctc_ch0_isr

0102: 8013 .dw ctc_ch1_isr

0104: 0014 .dw ctc_ch2_isr

0106: 8014 .dw ctc_ch3_isr

;---------------------------------------------------------------------

; Z80 Processor Test :

; :

; Description :

; Verify Z80 flags, registers (except IX/IY) and conditional :

; jumps, including all shadow register pairs. :

; :

; Adapted from IBM 5150 BIOS. :

;---------------------------------------------------------------------

0108: FFFFFFFF .align 0x100

010C: FF...

0200: proc_test

#local

0200: F3 di ; Ensure interrupts disabled

;---- First tests for normal flags register

0201: next_regs

0201: AF xor A, A

0202: 387E jr C, proc_test_err ; Carry should be clear

0204: E28202 jp PO, proc_test_err ; Parity should be even

0207: 2079 jr NZ, proc_test_err ; Result should be zero

0209: FA8202 jp M, proc_test_err ; Result should be positive

020C: D601 sub A, 1

020E: 3072 jr NC, proc_test_err ; Carry should be set

0210: EA8202 jp PE, proc_test_err ; Parity should be odd

0213: 286D jr Z, proc_test_err ; Result should be non-zero

0215: F28202 jp P, proc_test_err ; Result should be negative

0218: 3E01 ld A, 0x01

021A: CB3F srl A

021C: 3064 jr NC, proc_test_err ; Carry should be set

021E: 2062 jr NZ, proc_test_err ; Result should be zero

0220: CB17 rl A

0222: 385E jr C, proc_test_err ; Carry should be clear

0224: 285C jr Z, proc_test_err ; Result should be non-zero

;---- Repeat tests for shadow flags register

0226: 08 ex AF, AF'

0227: AF xor A, A

0228: 3858 jr C, proc_test_err ; Carry should be clear

022A: E28202 jp PO, proc_test_err ; Parity should be even

022D: 2053 jr NZ, proc_test_err ; Result should be zero

022F: FA8202 jp M, proc_test_err ; Result should be positive

0232: D601 sub A, 1

0234: 304C jr NC, proc_test_err ; Carry should be set

0236: EA8202 jp PE, proc_test_err ; Parity should be odd

0239: 2847 jr Z, proc_test_err ; Result should be non-zero

023B: F28202 jp P, proc_test_err ; Result should be negative

023E: 3E01 ld A, 0x01

0240: CB3F srl A

0242: 303E jr NC, proc_test_err ; Carry should be set

0244: 203C jr NZ, proc_test_err ; Result should be zero

0246: CB17 rl A

0248: 3838 jr C, proc_test_err ; Carry should be clear

024A: 2836 jr Z, proc_test_err ; Result should be non-zero

;---- Load a test pattern through all registers

024C: 3EFF ld A, 0xFF ; Setup one's pattern in A

024E: 37 scf

024F: ED47 ld I, A ; Write pattern through all regs

0251: ED57 ld A, I

0253: write_pattern

0253: 6F ld L, A

0254: 65 ld H, L

0255: 5C ld E, H

0256: 53 ld D, E

0257: 4A ld C, D

0258: 41 ld B, C

0259: 78 ld A, B

025A: D9 exx

025B: 6F ld L, A

025C: 65 ld H, L

025D: 5C ld E, H

025E: 53 ld D, E

025F: 4A ld C, D

0260: 41 ld B, C

0261: 3008 jr NC, proc_test_done

0263: 08 ex AF, AF'

0264: 78 ld A, B

0265: EEFF xor A, 0xFF ; Pattern make it through all regs

0267: 2019 jr NZ, proc_test_err ; If no, go to error

0269: 18E8 jr write_pattern

026B: proc_test_done

026B: B7 or A, A ; Resulting pattern is zero?

026C: C28202 jp NZ, proc_test_err ; If no, go to error

026F: 310000 ld SP, 0 ; Test all zeroes in SP

0272: 39 add HL, SP

0273: 7C ld A, H

0274: B5 or A, L

0275: 200B jr NZ, proc_test_err

0277: 31FFFF ld SP, 0xFFFF ; Test all ones in SP

027A: 39 add HL, SP

027B: 7C ld A, H

027C: AD xor A, L

027D: 2003 jr NZ, proc_test_err

027F: C38302 jp mem_test

0282: proc_test_err

0282: 76 halt ; Halt on error

#endlocal

;---------------------------------------------------------------------

; RAM Test :

; :

; Description :

; Performs a read/write storage test on RAM address space as :

; defined by RAM_BASE and RAM_SZ variables. :

; :

; Writes a series of patterns (0xAA, 0x55, 0xFF, 0x01 and 0x00) :

; and reads them back to check for errors. :

; :

; !!! DESTROYS CONTENTS OF ENTIRE MEMORY BLOCK !!! :

;---------------------------------------------------------------------

0283: mem_test

#local

0283: D9 exx

0284: 21A402 ld HL, mem_test_patterns ; Shadow HL holds ptr to patterns

0287: D9 exx

0288: 0605 ld B, 5 ; B holds outer loop (pattern) ctr

028A: mem_test_next

028A: 210060 ld HL, RAM_BASE ; Pointer to start of RAM

028D: 110020 ld DE, RAM_SZ ; Inner loop counter (size of RAM)

0290: D9 exx

0291: 7E ld A, (HL) ; Get test pattern for this round

0292: 23 inc HL ; Inc pointer to next test pattern

0293: D9 exx

0294: mem_test_loop

0294: 77 ld (HL), A ; Store pattern in memory

0295: AE xor A, (HL) ; XOR pattern out of memory

0296: 200B jr NZ, mem_test_err ; If not zero, error

0298: 23 inc HL ; Inc pointer to next memory loc

0299: 1B dec DE ; Dec inner loop

029A: 7A ld A, D ; Inner loop counter at zero?

029B: B3 or A, E

029C: 20F6 jr NZ, mem_test_loop ; No if NZ, next memory loc

029E: 10EA djnz mem_test_next ; Loop for next pattern

02A0: C30003 jp init ; All tests complete, init

02A3: mem_test_err

02A3: 76 halt ; Halt on error

02A4: AA55FF01 mem_test_patterns .dm 0xAA, 0x55, 0xFF, 0x01, 0

02A8: 00

#endlocal

;---------------------------------------------------------------------

; APPLICATION CODE :

;---------------------------------------------------------------------

#data RAM

; Mutexes

6000: 00 foreground_mtx .db 0 ; Which task owns the foreground.

; The foreground task can read

; buttons and update display row

; data.

; Semaphores

6001: 00 clock_app_sem .db 0

6002: 00 configr_app_sem .db 0

6003: 00 clock_upd_req_sem .db 0

6004: 00 clock_upd_sem .db 0

6005: 00000000 .align 0x10

6009: 00...

6010: 00000000 task_sched .ds 16 ; Each byte corresponds to one app

6014: 00...

; or task. A non-zero value

; indicates the app/task is

; scheduled to run.

; Display row/dot point buffers - keep each block contiguous!

.align 0x8

6020: 00000000 display_row1 .ds 8 ; Working buffers.

6024: 00000000

6028: 00000000 display_row2 .ds 8 ; Display rows will be refreshed

602C: 00000000

6030: 00000000 display_row3 .ds 8 ; using the data held in these

6034: 00000000

6038: 00 display_dp1 .db 0 ; buffers.

6039: 00 display_dp2 .db 0

603A: 00 display_dp3 .db 0

603B: 00000000 .align 0x8

603F: 00

6040: 00000000 staging_row1 .ds 8 ; Staging buffers.

6044: 00000000

6048: 00000000 staging_row2 .ds 8 ; New data to be displayed can be

604C: 00000000

6050: 00000000 staging_row3 .ds 8 ; staged in these buffers, then

6054: 00000000

6058: 00 staging_dp1 .db 0 ; copied to the working buffers

6059: 00 staging_dp2 .db 0 ; when ready for display.

605A: 00 staging_dp3 .db 0

#code ROM

02A9: FFFFFFFF .align 0x100

02AD: FF...

0300: init

0300: 31007F ld SP, RAM_end ; SP to top of RAM, below init'd

0303: 010001 ld BC, _INITIALIZER_size ; Copy initialised RAM from ROM

0306: 11007F ld DE, _INITIALIZED

0309: 21005F ld HL, _INITIALIZER

030C: CD0015 call memcpy

030F: AF xor A, A

0310: D3DE out (DEBUG_PORT), A ; Clear debug port display

; Zeroise RAM, -2 to save return addr on stack

0312: 01FE1E ld BC, RAM_size-2

0315: 210060 ld HL, RAM_BASE

0318: CD4015 call memset

;---- Configure CTC channels

; Configures CTC interrupt vector

031B: AF xor A, A

031C: D300 out (CTC_CH0), A

; Configures CTC Ch 1 - ~1ms delay for display refresh

031E: 3EA5 ld A, CTC_CH1_CFG

0320: D301 out (CTC_CH1), A

0322: 3E17 ld A, CTC_CH1_TCONST

0324: D301 out (CTC_CH1), A

; Configures CTC Ch 2 - ~10ms delay for scheduling various tasks

0326: 3EA5 ld A, CTC_CH2_CFG

0328: D302 out (CTC_CH2), A

032A: 3EEA ld A, CTC_CH2_TCONST

032C: D302 out (CTC_CH2), A

; Configures CTC Ch 3 as downcounter for RTC interrupt

032E: 3EC5 ld A, CTC_CH3_CFG

0330: D303 out (CTC_CH3), A

0332: 3E01 ld A, CTC_CH3_TCONST

0334: D303 out (CTC_CH3), A

;---- Configure the RTC

0336: 3E00 ld A, RTC_RATES_CFG ; WD and periodic int rates

0338: D31B out (RTC_RATES), A

033A: 3E08 ld A, RTC_INTS_CFG ; Interrupt enables

033C: D31C out (RTC_INTS), A

033E: 3E06 ld A, RTC_CTRL_CFG ; Control flags

0340: D31E out (RTC_CTRL), A

0342: AF xor A, A ; Configure alarm to occur each

0343: D311 out (RTC_SEC_ALM), A ; minute at 0 seconds.

0345: 3EC0 ld A, RTC_ALM_CFG

0347: D313 out (RTC_MIN_ALM), A

0349: D315 out (RTC_HRS_ALM), A

034B: D317 out (RTC_DAY_ALM), A

034D: DB1D in A, (RTC_FLAGS) ; Read RTC flags to clear them

; Configure and enable Z80 vectored interrupts

034F: ED5E im 2

0351: 3E01 ld A, VECTOR_INT_PG

0353: ED47 ld I, A

0355: FB ei

;---- Schedule applications to run

schedule_task APP_CLOCK

0356: E5 push HL

0357: 211360 ld HL, task_sched+APP_CLOCK

035A: 3603 ld (HL), APP_CLOCK

035C: E1 pop HL

schedule_task APP_CONFIGR

035D: E5 push HL

035E: 211460 ld HL, task_sched+APP_CONFIGR

0361: 3604 ld (HL), APP_CONFIGR

0363: E1 pop HL

0364: C30004 jp main_loop

;---- Main application loop

; Runs all scheduled tasks and applications.

0367: FFFFFFFF .align 0x100

036B: FF...