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Commits on Feb 23, 2021

• Merge pull request YosysHQ#595 from litghost/const_cell_info

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• Merge pull request YosysHQ#596 from litghost/make_clang_format

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• Update archapi.md with latest signature.

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• Change CellInfo in getBelPinsForCellPin to be const.

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• Run "make clangformat" to fix new Bits library.

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• Merge pull request YosysHQ#594 from YosysHQ/gatecat/heap-tidying

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• Refactor some common code to CellInfo methods

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• HeAP: Document legalise_placement_strict better

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• nexus: Fix getPipDelay returning negative after refactor

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Commits on Feb 22, 2021

• pyconsole: Avoid lockup when reading from stdin

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Commits on Feb 20, 2021

• Demote the 'no clocks' warning to info and make clearer

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• Merge pull request YosysHQ#592 from YosysHQ/gatecat/rework-delay

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• Update generic.md

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Commits on Feb 19, 2021

• clangformat

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• python: Bindings for DelayPair and DelayQuad

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• Replace DelayInfo with DelayPair/DelayQuad

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• Add DelayPair and DelayQuad structures

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• Merge pull request YosysHQ#576 from litghost/add_cell_bel_pin_mapping

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Commits on Feb 18, 2021

• Fix sign mismatch.

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• Do some spell checking on site_router.cc

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• Add some utility methods for site instance access.

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• Update README's with latest instructions and features.

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• Merge pull request YosysHQ#588 from YosysHQ/gatecat/gowin-fixes

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• Merge pull request YosysHQ#590 from cbalint13/master

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Commits on Feb 17, 2021

• Expose ice40 arch placer-heap internal parameters.

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• Update tests library to include Bits unit test.

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• Add utility targets for getting plain text outputs.

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• Add IOSTANDARD to ports.

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• Emit fixed attributes to output physical netlist.

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• Use Bits library for bit instrisics.

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• Refactor "get only from iterator" to a utility.

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• Keep all build artifacts under create_bba/build.

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• Change how package pin IO sites are selected.

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• Change makefiles to build a FPGA interchange BBA.

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• Add examples invoking FPGA interchange nextpnr.

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