Update the UART Rx

schoeberl · Oct 31, 2024 · b8fe3c1 · b8fe3c1
1 parent dda097b
commit b8fe3c1
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Showing 2 changed files with 19 additions and 19 deletions.
diff --git a/chisel-book.tex b/chisel-book.tex
@@ -5341,10 +5341,10 @@ \subsection{Parameterizing FIFOs}
 We define an \code{abstract}
 FIFO class as a \myref{https://docs.scala-lang.org/tour/generic-classes.html}{generic class}
 with a Chisel type \code{T} as parameter to be able to buffer
-any Chisel data type. In the abstract class we also test that the
+any Chisel data type (see Listing~\ref{lst:fifo:abstract}). In the abstract class we also test that the
 parameter \code{depth} has a useful value.
 
-\shortlist{code/fifo_abstract.txt}
+\longlist{code/fifo_abstract.txt}{Abstract class for FIFO veriations.}{lst:fifo:abstract}
 
 In Section~\ref{sec:fifo} we defined our own types for the interface with common
 names for signals, such as \code{write}, \code{full}, \code{din}, \code{read},

diff --git a/src/main/scala/uart/uart.scala b/src/main/scala/uart/uart.scala
@@ -76,39 +76,39 @@ class Rx(frequency: Int, baudRate: Int) extends Module {
     val channel = new UartIO()
   })
 
-  val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U
-  val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 1).U
+  val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1)
+  val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 2) // -2 for the falling delay
 
-  // Sync in the asynchronous RX data, reset to 1 to not start reading after a reset
-  val rxReg = RegNext(RegNext(io.rxd, 1.U), 1.U)
+  // Sync in the asynchronous RX data
+  val rxReg = RegNext(RegNext(io.rxd, 0.U), 0.U)
+  val falling = !rxReg && (RegNext(rxReg) === 1.U)
 
   val shiftReg = RegInit(0.U(8.W))
-  val cntReg = RegInit(0.U(20.W))
+  val cntReg = RegInit(BIT_CNT.U(20.W)) // have some idle time before listening
   val bitsReg = RegInit(0.U(4.W))
-  val validReg = RegInit(false.B)
+  val valReg = RegInit(false.B)
 
   when(cntReg =/= 0.U) {
     cntReg := cntReg - 1.U
-  } .elsewhen(bitsReg =/= 0.U) {
-    cntReg := BIT_CNT
-    shiftReg := rxReg ## (shiftReg >> 1)
+  }.elsewhen(bitsReg =/= 0.U) {
+    cntReg := BIT_CNT.U
+    shiftReg := Cat(rxReg, shiftReg >> 1)
     bitsReg := bitsReg - 1.U
-    // the last bit shifted in
+    // the last shifted in
     when(bitsReg === 1.U) {
-      validReg := true.B
+      valReg := true.B
     }
-  } .elsewhen(rxReg === 0.U) {
-    // wait 1.5 bits after falling edge of start
-    cntReg := START_CNT
+  }.elsewhen(falling) { // wait 1.5 bits after falling edge of start
+    cntReg := START_CNT.U
     bitsReg := 8.U
   }
 
-  when(validReg && io.channel.ready) {
-    validReg := false.B
+  when(valReg && io.channel.ready) {
+    valReg := false.B
   }
 
   io.channel.bits := shiftReg
-  io.channel.valid := validReg
+  io.channel.valid := valReg
 }
 //- end