Tests for RWTapping aggregates (chipsalliance#3443)

* add aggregate tapping unit tests * add element accesses of probes to tests * cleanup dontcares
rahiCICD · Aug 8, 2023 · 6c7be5d · 6c7be5d
1 parent da90c5b
commit 6c7be5d
Showing 1 changed file with 63 additions and 0 deletions.
diff --git a/src/test/scala/chiselTests/BoringUtilsTapSpec.scala b/src/test/scala/chiselTests/BoringUtilsTapSpec.scala
@@ -228,4 +228,67 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
     e.getMessage should include("Cannot drill writable probes upwards.")
   }
 
+  it should "work when tapping an element within a Bundle" in {
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(
+      new RawModule {
+        class MiniBundle extends Bundle {
+          val x = Bool()
+        }
+        class Child() extends RawModule {
+          val b = Wire(new MiniBundle)
+        }
+
+        val child = Module(new Child())
+
+        // directly tap Bundle element
+        val outRWProbe = IO(probe.RWProbe(Bool()))
+        probe.define(outRWProbe, BoringUtils.rwTap(child.b.x))
+
+        // tap Bundle, then access element
+        val outRWBundleProbe = IO(probe.RWProbe(new MiniBundle))
+        val outElem = IO(probe.RWProbe(Bool()))
+        probe.define(outRWBundleProbe, BoringUtils.rwTap(child.b))
+        probe.define(outElem, outRWBundleProbe.x)
+      }
+    )
+    matchesAndOmits(chirrtl)(
+      "wire b : { x : UInt<1>}",
+      "define bore = rwprobe(b.x)",
+      "define bore_1 = rwprobe(b)",
+      "define outRWProbe = child.bore",
+      "define outRWBundleProbe = child.bore_1",
+      "define outElem = outRWBundleProbe.x"
+    )()
+  }
+
+  it should "work when tapping an element within a Vec" in {
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(
+      new RawModule {
+        class Child() extends RawModule {
+          val b = Wire(Vec(4, Bool()))
+        }
+
+        val child = Module(new Child())
+
+        // directly tap Vec element
+        val outRWProbe = IO(probe.RWProbe(Bool()))
+        probe.define(outRWProbe, BoringUtils.rwTap(child.b(2)))
+
+        // tap Vec, then access element
+        val outRWVecProbe = IO(probe.RWProbe(Vec(4, Bool())))
+        val outElem = IO(probe.RWProbe(Bool()))
+        probe.define(outRWVecProbe, BoringUtils.rwTap(child.b))
+        probe.define(outElem, outRWVecProbe(1))
+      }
+    )
+    matchesAndOmits(chirrtl)(
+      "wire b : UInt<1>[4]",
+      "define bore = rwprobe(b[2])",
+      "define bore_1 = rwprobe(b)",
+      "define outRWProbe = child.bore",
+      "define outRWVecProbe = child.bore_1",
+      "define outElem = outRWVecProbe[1]"
+    )()
+  }
+
 }