diff --git a/dev_root/controller/ports.py b/dev_root/controller/ports.py
index 9850fec..ea634b8 100644
--- a/dev_root/controller/ports.py
+++ b/dev_root/controller/ports.py
@@ -44,7 +44,7 @@ def __init__(self, target, gc, bfrt_info):
         self.loopback_ports = []
 
         # PktGen table to configure pktgen ports in loopback mode
-        self.pktgen_port_cfg_table = bfrt_info.table_get('$PKTGEN_PORT_CFG')
+        self.pktgen_port_cfg_table = bfrt_info.table_get('tf1.pktgen.port_cfg')
 
     def get_dev_port(self, fp_port, lane):
         ''' Convert front-panel port to dev port.
diff --git a/dev_root/p4/README.md b/dev_root/p4/README.md
index 5b550f1..2ce0f64 100644
--- a/dev_root/p4/README.md
+++ b/dev_root/p4/README.md
@@ -3,7 +3,7 @@
 The SwitchML P4 program is written in P4-16 for the [Tofino Native Architecture (TNA)](https://github.com/barefootnetworks/Open-Tofino) and the controller uses the Barefoot Runtime Interface (BRI) to program the switch.
 
 ## 1. Requirements
-The P4 code has been tested on Intel P4 Studio 9.6.0.
+The P4 code has been tested on Intel P4 Studio 9.9.0.
 
 For details on how to obtain and compile P4 Studio, we refer you to the official [Intel documentation](https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch.html).
 
@@ -67,4 +67,4 @@ With RDMA, the packet layout is slightly different depending on which part of a
 The P4 program does not check nor update the ICRC value, so the end-host servers should disable ICRC checking.
 
 ## References
-<a id="1">[1]</a> Intel® P4 Studio Software Development Environment (SDE) 9.6.0 Installation Guide
+<a id="1">[1]</a> Intel® P4 Studio Software Development Environment (SDE) Installation Guide