Updated covergen to not include stores as they are incomplete.

Modified makefile riscv-dv to not simulation only generate tests.
openhwgroup · Jun 19, 2024 · 9e93f21 · 9e93f21
1 parent 685f4d3
commit 9e93f21
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Showing 3 changed files with 4 additions and 59 deletions.
diff --git a/Makefile b/Makefile
@@ -55,8 +55,8 @@ riscvdv:
 #	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
 #	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
 #	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
-	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
-	cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
+	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	#cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
 
 riscvdv_functcov:
 	mkdir -p ${SIM}/questa/functcov_logs

diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh
diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py
@@ -60,8 +60,8 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor
     lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
   elif (test in stypes):#["sb", "sh", "sw", "sd"]
     #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
-    lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
-    #print("Error: %s type not implemented yet" % test)
+    #lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
+    print("Error: %s type not implemented yet" % test)
   elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
     if (randint(1,100) > 50):
       rs1val = rs2val