Allow LW opcode; report disallowed opcodes at parse time (FuelLabs#471)

* Allow LW opcode; report disallowed opcodes at parse time * fix register allocation issue for aloc opcode
mitchmindtree · Dec 17, 2021 · fbc9613 · fbc9613
1 parent 2639c11
commit fbc9613
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Showing 5 changed files with 64 additions and 17 deletions.
diff --git a/core_lang/src/asm_generation/expression/mod.rs b/core_lang/src/asm_generation/expression/mod.rs
@@ -157,6 +157,24 @@ pub(crate) fn convert_expression_to_asm<'sc>(
             // For each opcode in the asm expression, attempt to parse it into an opcode and
             // replace references to the above registers with the newly allocated ones.
             for op in body {
+                /*
+                errors.append(
+                    &mut op
+                        .op_args
+                        .iter()
+                        .filter_map(|Ident { primary_name, span }| {
+                            if mapping_of_real_registers_to_declared_names
+                                .get(primary_name)
+                                .is_none() &&
+                            {
+                                Some(todo!("error! {:?}", primary_name))
+                            } else {
+                                None
+                            }
+                        })
+                        .collect::<Vec<_>>(),
+                );
+                */
                 let replaced_registers = op.op_args.iter().map(|x| -> Result<_, CompileError> {
                     match realize_register(
                         x.primary_name,

diff --git a/core_lang/src/asm_lang/mod.rs b/core_lang/src/asm_lang/mod.rs
@@ -539,16 +539,22 @@ impl<'sc> Op<'sc> {
                     VirtualOp::CTMV(r1, r2)
                 }
                 "ji" => {
-                    errors.push(CompileError::DisallowedJi {
-                        span: name.span.clone(),
-                    });
-                    return err(warnings, errors);
+                    let imm = check!(
+                        single_imm_24(args, immediate, whole_op_span),
+                        return err(warnings, errors),
+                        warnings,
+                        errors
+                    );
+                    VirtualOp::JI(imm)
                 }
                 "jnei" => {
-                    errors.push(CompileError::DisallowedJnei {
-                        span: name.span.clone(),
-                    });
-                    return err(warnings, errors);
+                    let (r1, r2, imm) = check!(
+                        two_regs_imm_12(args, immediate, whole_op_span),
+                        return err(warnings, errors),
+                        warnings,
+                        errors
+                    );
+                    VirtualOp::JNEI(r1, r2, imm)
                 }
                 "ret" => {
                     let r1 = check!(
@@ -596,10 +602,13 @@ impl<'sc> Op<'sc> {
                     VirtualOp::LB(r1, r2, imm)
                 }
                 "lw" => {
-                    errors.push(CompileError::DisallowedLw {
-                        span: name.span.clone(),
-                    });
-                    return err(warnings, errors);
+                    let (r1, r2, imm) = check!(
+                        two_regs_imm_12(args, immediate, whole_op_span),
+                        return err(warnings, errors),
+                        warnings,
+                        errors
+                    );
+                    VirtualOp::LW(r1, r2, imm)
                 }
                 "aloc" => {
                     let r1 = check!(

diff --git a/core_lang/src/asm_lang/virtual_ops.rs b/core_lang/src/asm_lang/virtual_ops.rs
@@ -177,7 +177,7 @@ impl VirtualOp {
             LB(r1, r2, _i) => vec![r1, r2],
             LWDataId(r1, _i) => vec![r1],
             LW(r1, r2, _i) => vec![r1, r2],
-            ALOC(_imm) => vec![],
+            ALOC(r1) => vec![r1],
             MCL(r1, r2) => vec![r1, r2],
             MCLI(r1, _imm) => vec![r1],
             MCP(r1, r2, r3) => vec![r1, r2, r3],

diff --git a/core_lang/src/parse_tree/expression/asm.rs b/core_lang/src/parse_tree/expression/asm.rs
@@ -147,6 +147,7 @@ impl<'sc> AsmOp<'sc> {
             warnings,
             errors
         );
+        errors.append(&mut disallow_opcode(&opcode));
         let mut args = vec![];
         let mut immediate_value = None;
         for pair in iter {
@@ -230,3 +231,22 @@ impl<'sc> AsmRegisterDeclaration<'sc> {
         ok(reg_buf, warnings, errors)
     }
 }
+
+fn disallow_opcode<'sc>(op: &Ident<'sc>) -> Vec<CompileError<'sc>> {
+    let mut errors = vec![];
+
+    match op.primary_name.to_lowercase().as_str() {
+        "jnei" => {
+            errors.push(CompileError::DisallowedJnei {
+                span: op.span.clone(),
+            });
+        }
+        "ji" => {
+            errors.push(CompileError::DisallowedJi {
+                span: op.span.clone(),
+            });
+        }
+        _ => (),
+    };
+    errors
+}
diff --git a/lib-std/src/chain.sw b/lib-std/src/chain.sw
@@ -53,14 +53,14 @@ pub fn panic(code: u64) {
 // TODO some safety checks on the input data? We are going to assume it is the right type for now.
 pub fn get_script_data<T>() -> T {
     asm(script_data_len, to_return, script_data_ptr, script_len, script_len_ptr: 376, script_data_len_ptr: 384) {
-        lw script_len script_len_ptr;
-        lw script_data_len script_data_len_ptr;
+        lw script_len script_len_ptr i0;
+        lw script_data_len script_data_len_ptr i0;
         // get the start of the script data
         // script_len + script_start
         add script_data_ptr script_len is;
         // allocate memory to copy script data into
-        mv to_return sp;
-        cfe script_data_len;
+        aloc script_data_len;
+        move to_return sp;
         // copy script data into above buffer
         mcp to_return script_data_ptr script_data_len;
         to_return: T