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Text about capability tags in HyperRAM needs updating

Status: Open.

#384 In lowRISC/sonata-system;

· rmn30 opened on Jan 27, 2025

Debug host access to HyperRAM?

Status: Open.

#381 In lowRISC/sonata-system;

· nwf opened on Jan 22, 2025

IP to suspend/reset on both FPGA and sim

Status: Open.

#380 In lowRISC/sonata-system;

· marnovandermaas opened on Jan 17, 2025

Mistaken use of variable assignment in ibex_cs_registers.sv

Status: Open.

#378 In lowRISC/sonata-system;

· chris-stafford-64 opened on Jan 8, 2025

OpenOCD "load_image" also sets the chip running?

Status: Open.

#373 In lowRISC/sonata-system;

· nwf opened on Dec 19, 2024

SRAM block list needs to be updated in docs

Status: Open.

#352 In lowRISC/sonata-system;

· marnovandermaas opened on Nov 12, 2024

Describe the pinmux generation and design in documentation.

Status: Open.

#349 In lowRISC/sonata-system;

· marnovandermaas opened on Nov 12, 2024

Rename xbar_main.json to xbar_main.json.tpl. Then rename xbar_main_generated.hjson to xbar_main.json.

Status: Open.

#348 In lowRISC/sonata-system;

· marnovandermaas opened on Nov 12, 2024

Inconsistent timing results/failed timing on newer Vivado versions

Status: Open.

#289 In lowRISC/sonata-system;

· GregAC opened on Oct 29, 2024

Ethernet smoke test

Status: Open.

#253 In lowRISC/sonata-system;

· marnovandermaas opened on Oct 16, 2024

[CI] Enable cherirtos testsuite on the FPGA Job

Status: Open.

#250 In lowRISC/sonata-system;

· engdoreis opened on Oct 16, 2024

CHERI sanity test has an illegal instruction

Status: Open.

#206 In lowRISC/sonata-system;

· marnovandermaas opened on Sep 25, 2024