******** README ********

NOTE:- We are only submitting the verilog .v source files i.e. the VIVADO Design sources.The complete vivado project is available at https://www.github.com/hansinahuja/32-Bit-ALU.git . It can be made public on demand.

CS203: Digital Logic Design

Instructor: Dr. Neeraj Goel

Project: 32 Bit ALU

Contributors: Hansin Ahuja (2018csb1094)

Paras Goyal (2018csb1111)

*** Features ***

1) Fast adder: control 0

2) Multiplier: control 1

3) Subtractor: control 2

4) Logical left shift: control 3

5) Logical right shift: control 4

6) Arithmetic right shift: control 5

7) Bitwise AND: control 6

8) Bitwise OR: control 7

9) Bitwise NOT: control 8

10) Bitwise XOR: control 9

11) Comparison: control 10

*** How to run ***

The module 'main.v' takes 3 inputs:

1) A 32 bit

2) B 32 bit

3) control 4 bit

and gives 6 outputs:

1) S 32 bit

2) carry 1 bit

3) overflow 1 bit

4) lessthan 1 bit

5) equalto 1 bit

6) zero 1 bit

*** Behaviour ***

1) S: stores result of the operation performed on A and B as indicated by the control input. The operation is only performed on input A if is a single input function, i.e. bitwise shift or bitwise NOT.

2) carry:

if control = 0: stores carry generated by addition of A and B

else if control = 2: stores carry generated by 2s complement subtraction of A and B, ie carry = 1 for a positive result and carry = 0 for a negative result

else: carry = 0

3) overflow:

if control = 1: overflow = 1 if multiplication of A and B yields a result which cannot be stored in 32 bits or if the result of multiplication is a negative number (33rd Bit is considered as sign bit here). Else, overflow = 0.

else: overflow = 0

4) lessthan:

if control = 10: lessthan = 1 if A < B. Else, lessthan = 0.

else: lessthan = 0

5) equalto:

if control = 10: lessthan = 1 if A = B. Else, lessthan = 0.

else: lessthan = 0

6) zero:

= 1 if S = 0 and control != 10

= 0 if S != 0 or control = 10