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Error while mapping cells #12

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Enamak opened this issue Oct 6, 2018 · 9 comments
Open

Error while mapping cells #12

Enamak opened this issue Oct 6, 2018 · 9 comments

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@Enamak
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Enamak commented Oct 6, 2018 •
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Hi, I was trying to execute a simple circuit with flip-flops, as shown below:

input clk, rst;
input [3:0] g_input, e_input; 
wire [3:0] g_input, e_input; 
output [3:0] o; 
reg [3:0] o;

generate
    always@(posedge clk or posedge rst) begin
        if(rst) begin
	    o <= 0;
	end else begin
	    o <= g_input;
	end
    end
endgenerate

Which worked fine when testing with the SCD Evaluator, for 5 cycles, g_input = 1234 and e_input = 0000, the separatedoutput was 0, 4, 3, 2, 1, as expected. As soon as I added an if inside the else statement, like:

if(g_input == 4'b0110) o <= g_input;
else o <= e_input;

yosys would fail at the techmap step, with the following error:


ERROR: Found error in internal cell \main.$eq$teste.v:15$2.B_conv ($bu0) at kernel/rtlil.cc:1118:
  attribute \src "teste.v:15|stdcells_S.v:576"
  cell $bu0 $eq$teste.v:15$2.B_conv
    parameter \Y_WIDTH 4
    parameter \A_WIDTH 4
    parameter \A_SIGNED 0
    connect \Y $eq$teste.v:15$2.B_buf
    connect \A 4'0110
  end

If instead of the == a > or >= operator was used, another error would occur, at ABC step this time:

ABC: Warning: The network was strashed and balanced before mapping.
ABC: + write_blif <abc-temp-dir>/output.blif
ERROR: Syntax error in line 6!

Finally, if the < or <= operator was used, it would compile fine into netlist, but the output of the SCD when testing it with the evaluator would come totally off, almost like inversed (it would invert the if, and the default value for 'o' port would be F instead of 0).

I used the sum.yos script found at circuit_synthesis/sum/.
Also, the DFF cells of the netlist files are being generated without the port 'I', which I had to add manually to each cell for V2SCD to work.

All of the examples ran fine with Test Bench. Am I missing something?

Thanks,
Gonçalo
@Enamak
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Enamak commented Oct 16, 2018

Functions like a full adder made for one cycle only did not work as well. It looks like yosys is not mapping correctly all the cells. I also tried using sum.v and mult.v files (used the commented code and CC=1 for both), located at circuit_synthesis/sum/ and circuit_synthesis/mult/, respectively, to see if it was a problem with my code, but in the end, both gave wrong outputs when testing with SCDEvaluator. With a cc greater than one, when compiling the mult file, it would fail at the techmap step, with an error similar as the one in the first post.

ERROR: Found error in internal cell \moda.$techmap$mul$teste.v:29$1.arraymul.$shl$stdcells_S.v:786$338.expand ($bu0) at kernel/rtlil.cc:1118:
  attribute \src "teste.v:29|stdcells_S.v:811|stdcells_S.v:786|stdcells_S.v:177"
  cell $bu0 $techmap$mul$teste.v:29$1.arraymul.$shl$stdcells_S.v:786$338.expand
    parameter \Y_WIDTH 129
    parameter \A_WIDTH 129
    parameter \A_SIGNED 0
    connect \Y $techmap$mul$teste.v:29$1.arraymul.$shl$stdcells_S.v:786$338.chain [128:0]
    connect \A $mul$teste.v:29$1.B_buf
  end

Any feedback would be appreciated.

@siamumar
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The issue with the combinational circuit is fixed. Please pull and check. We are working on the issue with sequential circuits now. Apologies for the delay.

@Enamak
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Enamak commented Oct 23, 2018

No problem at all.
I tested the sum.v and mult.v combinational circuits and they worked fine, I'll be waiting for the sequential fix.
Thanks for the help.

@siamumar
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The sequential circuit works now. But with Yosys, only reset value of 0 is supported. This should work for most of the functions including sum.

@Enamak
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Enamak commented Oct 30, 2018

Sorry for the delay.
I tested the sum.v sequential circuit and it worked fine with the SCD_Evaluator_Main, although when using TinyGarble itself, it wouldn't be precise at all. It would print the right output most of the times, sometimes only half, and the rest of the times it would print random values. I also ran the combinational sum one once more, but now several times, and it also happened.
Using the hamming function with the example shown on TinyGarble's git README also gave the same result.
Thanks for the help so far.

@Enamak
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Enamak commented Nov 19, 2018

Update: The problem I mentioned on the last post it's probably being caused by the OT, since when i disabled it when running TinyGarble it gave the right output everytime.

@siamumar
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Hi sorry again for the late reply. I could not reproduce the issue here. Both sum and Hamming work with OT. Can you please make a fresh copy and see if the error still occurs?
The OT implementation uses the OpenSSL library. Please make sure it is properly installed.
Please let me know the updates.

@Enamak
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Enamak commented Dec 5, 2018

No problem! Thanks for the help so far, and sorry for taking so long to answer.
I did a clean install of ubuntu but it still didn't fix the problem.
The cmake output i get is:

-- The CXX compiler identification is GNU 7.3.0
-- Check for working CXX compiler: /usr/bin/c++
-- Check for working CXX compiler: /usr/bin/c++ -- works
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Detecting CXX compile features
-- Detecting CXX compile features - done
Release build.
-- Boost version: 1.65.1
-- Found the following Boost libraries:
--   program_options
-- Found OpenSSL: /usr/lib/x86_64-linux-gnu/libcrypto.so (found version "1.0.2n") 
-- Configuring done
-- Generating done

@siamumar
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I am not sure how I missed this comment! I sincerely apologize for this.

Please use the versions mentioned in the ReadMe file: OpenSSL (1.0.1f <), boost(1.55.0 <), and cmake (3.1.0 <).

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@siamumar @Enamak