pareto_pwr_mse

Selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
add8s_83C	0.00	0.00	0.00	0.00	0	[Verilog] [C]
add8s_6FR	0.39	1.56	37.30	1.48	0.7	[Verilog] [C]
add8s_6QJ	1.17	3.91	79.44	7.44	3.7	[Verilog] [C]
add8s_6UN	1.88	5.47	87.50	11.76	8.4	[Verilog] [C]
add8s_6TN	3.67	10.16	94.56	19.71	31	[Verilog] [C]
add8s_6YE	6.41	14.06	97.20	39.40	89	[Verilog] [C]
add8s_70S	10.08	35.16	97.84	49.43	240	[Verilog] [C]
add8s_70F	16.48	54.69	98.32	68.05	684	[Verilog] [C]
add8s_6R6	28.83	84.38	99.22	202.19	1995	[Verilog] [C]
add8s_6HF	44.45	100.00	99.48	99.98	4551	[Verilog] [C]

V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020