Commits

Breadcrumbs

History for

onrefs/heads/pypi

User selector

All users

Datepicker

All time

Commit History

Commits on Dec 13, 2024

• pypi version

  mrazekv

  committed
  2403202

Commits on Oct 3, 2024

• Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel

  mrazekv

  committed
  813f111

• CGP with more than 26 inputs naming

  mrazekv

  committed
  c1e8680

Commits on Oct 1, 2024

• Added ripple borrow subtractor circuit and updated automated testing.

  honzastor

  committed
  b87f835

Commits on Jul 22, 2024

• reconnected wire was not identified as a bus

  mrazekv

  committed
  bc95444

• bug in cgp indexes with constant wires, they were encouted

  mrazekv

  committed
  04cd3e4

Commits on Jul 18, 2024

• signed version of python code

  mrazekv

  committed
  f34471b

• CGP circuit accepts BUS inputs

  mrazekv

  committed
  4cd1189

Commits on Jul 9, 2024

• ripple cary subtractor

  mrazekv

  committed
  bc0104d

Commits on Jul 8, 2024

• Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel

  mrazekv

  committed
  e41b4a2

• popcount parent component

  mrazekv

  committed
  c480eea

Commits on Apr 17, 2024

• Fixed hierarchical BLIF generation for popcount_compare.

  honzastor

  committed
  ce36ebf

Commits on Apr 14, 2024

• Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

  honzastor

  committed
  6003886

Commits on Apr 13, 2024

• Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.

  honzastor

  committed
  97e79b9

Commits on Apr 8, 2024

• Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.

  honzastor

  committed
  739d5fa

• popcount with variable sizes

  mrazekv

  committed
  4e331f0

Commits on Apr 5, 2024

• popcount fixes

  mrazekv

  committed
  128b130

• Merge branch 'popcount' into devel

  mrazekv

  authored
  1219d7b

• Popcount implementation

  mrazekv

  committed
  2cf7b92

Commits on Mar 27, 2024

• Added instantiation of wires and buses from inputs. Hopefully fixed now.

  honzastor

  committed
  da733cf

• Additional type hint fix.

  honzastor

  committed
  21a6437

• Type hint bugfix for pytest.

  honzastor

  committed
  73101eb

• Added unsigned recursive multiplier and made some bugfixes.

  honzastor

  committed
  d013a40

Commits on Mar 22, 2024

• popcount and compare

  mrazekv

  committed
  2e1694c

Commits on Mar 5, 2024

• Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation.

  honzastor

  committed
  7e1112c

Commits on Apr 13, 2023

• CGP circuit checks

  mrazekv

  committed
  f853a46

Commits on Mar 28, 2023

• Implementation of QuAd approximate adder

  mrazekv

  committed
  a44b063

• connection checks (asserts)

  mrazekv

  committed
  a4741db

Commits on Mar 24, 2023

• MUX support of constant values

  mrazekv

  committed
  44e0a92

Commits on Mar 23, 2023

• accepts a wire as a bus

  mrazekv

  committed
  49bbc86

Commits on Mar 22, 2023

• Bugfix in conditional statement.

  honzastor

  committed
  7cf34d0

• Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

  honzastor

  committed
  b88c502

Commits on Feb 24, 2023

• Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

  honzastor

  committed
  d52e67b

Commits on Feb 22, 2023

• Merge branch 'main' into devel

  mrazekv

  authored
  283f9c7

• Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel

  mrazekv

  committed
  6dd69c5

Pagination

PreviousNext