Skip to content
View defacedef1's full-sized avatar

Block or report defacedef1

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. skywater-pdk skywater-pdk Public

    Forked from google/skywater-pdk

    Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

    Python

  2. OpenLane OpenLane Public

    Forked from efabless/OpenLane

    NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Mag…

    Verilog

  3. caravel caravel Public

    Forked from efabless/caravel_mpw-one

    Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

    Verilog

  4. mpw_precheck mpw_precheck Public

    Forked from efabless/mpw_precheck

    Python

  5. sv2v sv2v Public

    Forked from zachjs/sv2v

    SystemVerilog to Verilog conversion

    Haskell

  6. Silice Silice Public

    Forked from sylefeb/Silice

    Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

    C++