Generated files (.sdf, .v) for sims are located in designs/serializer/sim

Source files (.v) are located in designs/serializer/src

config.json is located in designs/serializer

OpenSERDES Serializer design variations:

serializer_unit_cell (original)

serializer_unit_cell_mod (modified)

serializer_unit_cell_16 (16-bit)

Conventional Tree Serializer design variations:

conv_tree_serializer

conv_tree_serializer_16

Low Power Tree Serializer design:

lp_tree_serializer

Simulations are run in the simulation/sim directory.

For each make command, specify TOP=<serializer_version>, where <serializer_version> is serdes for OpenSERDES, conv_tree_serializer for the conventional tree, and lp_tree_serializer for the low power tree. For pre-synthesis simulations, use TOP=<serializer_version>.presyn

Make all will run vcs and validate text file output is correct.

Make vcs will run the corresponding testbench module that tests 10 random inputs and outputs a waveform and text file of serializer inputs and outputs. Post-synthesis simulations include sdf annotations.

Make compare will run check_output.py to check that text file output is correct

Make wave will open the waveform with silicon explorer

Submodule testbenches are in simulation/src/tb/submodule and include files are in simulation/sim/submodule.

Archived top-level testbenches are in simulation/src/tb/archive and their include files are in simulation/sim/archive.

Note that post-apr verification for lp_tree_serializer doesn?t exist because tri-state buffers output Z instead of holding state when disabled. Pre-synthesis verification using latch behavior was determined to be sufficient for our purposes. Materials from our attempts to use hspice to run analog simulations are in simulation/sim/hspice.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII.

You can check out the documentation, including in-depth guides and reference manuals at ReadTheDocs.

If you just want to try OpenLane out, try this Colaboratory by our friends at Google and ChipsAlliance. It's an online Python-based utility, and the best part is, you don't need to install anything.

The short version is, to install the OpenLane environment...

On Windows, install and launch the Windows Subsystem for Linux before doing anything. We recommend and provide instructions for Ubuntu 20.04.

On macOS, get brew.

1. Get Docker (or a compatible container engine)
   • On Ubuntu, follow the Docker post install instructions after you install Docker.
2. Get Python 3.6 or higher (macOS | Ubuntu)
   • On Ubuntu, you may also need to install venv: apt-get install python3-venv, and pip: apt-get install python3-pip.
3. Get git (macOS | Ubuntu)
4. Get GNU Make (macOS | Ubuntu)

Run the following commands in your command-line prompt:

cd $HOME
git clone https://github.com/The-OpenROAD-Project/OpenLane
cd OpenLane
make
make test

If everything's gone smoothly, that's it. OpenLane is set up on your computer. To enter the OpenLane environment, cd $HOME/OpenLane and then make mount.

See the installation docs at https://openlane.readthedocs.io/en/latest/getting_started/installation/index.html.

After entering the OpenLane environment, you can start hardening chips: the following command, for example, runs the included spm design.

./flow.tcl -design spm

You can join the Open Source Silicon Slack, where you can ask thousands of other open source hardware enthusiasts for help with setting up or running OpenLane.

The Apache License, version 2.0.

Docker images distributed by Efabless Corporation under the same license.

Binaries in OpenLane distributions may fall under stricter open source licenses.