Implement pslldq

Fixes ish-app#863
Sekedo664 · Aug 22, 2020 · 5dcfeab · 5dcfeab
1 parent 4bc45e2
commit 5dcfeab
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Showing 6 changed files with 38 additions and 10 deletions.
diff --git a/emu/cpu.h b/emu/cpu.h
@@ -15,6 +15,7 @@ union mm_reg {
     dword_t dw[2];
 };
 union xmm_reg {
+    unsigned __int128 u128;
     qword_t qw[2];
     uint32_t u32[4];
     uint16_t u16[8];

diff --git a/emu/decode.h b/emu/decode.h
@@ -294,12 +294,12 @@ __no_instrument DECODER_RET glue(DECODER_NAME, OP_SIZE)(DECODER_ARGS) {
 
                 case 0x73: READMODRM_NOMEM;
                            switch (modrm.opcode) {
-                               case 0x02: TRACEI("psrlq imm, xmm");
-                                          READIMM8; V_OP(imm_shiftr_q, imm, xmm_modrm_reg, 128); break;
-
-                               case 0x06: TRACEI("psllq imm, xmm");
-                                          READIMM8; V_OP(imm_shiftl_q, imm, xmm_modrm_reg, 128); break;
-
+                               case 2: TRACEI("psrlq imm, xmm");
+                                       READIMM8; V_OP(imm_shiftr_q, imm, xmm_modrm_reg, 128); break;
+                               case 6: TRACEI("psllq imm, xmm");
+                                       READIMM8; V_OP(imm_shiftl_q, imm, xmm_modrm_reg, 128); break;
+                               case 7: TRACEI("pslldq imm, xmm");
+                                       READIMM8; V_OP(imm_shiftl_dq, imm, xmm_modrm_reg, 128); break;
                                default: UNDEFINED;
                            }
                            break;

diff --git a/emu/vec.c b/emu/vec.c
@@ -61,6 +61,13 @@ void vec_imm_shiftr_q64(NO_CPU, const uint8_t amount, union mm_reg *dst) {
         dst->qw >>= amount;
 }
 
+void vec_imm_shiftl_dq128(NO_CPU, uint8_t amount, union xmm_reg *dst) {
+    if (amount >= 16)
+        zero_xmm(dst);
+    else
+        dst->u128 <<= amount * 8;
+}
+
 void vec_shiftl_q128(NO_CPU, union xmm_reg *amount, union xmm_reg *dst) {
     uint64_t amount_qw = amount->qw[0];
 

diff --git a/emu/vec.h b/emu/vec.h
@@ -22,6 +22,7 @@ void vec_imm_shiftl_q128(NO_CPU, const uint8_t amount, union xmm_reg *dst);
 void vec_imm_shiftl_q64(NO_CPU, const uint8_t amount, union mm_reg *dst);
 void vec_imm_shiftr_q128(NO_CPU, const uint8_t amount, union xmm_reg *dst);
 void vec_imm_shiftr_q64(NO_CPU, const uint8_t amount, union mm_reg *dst);
+void vec_imm_shiftl_dq128(NO_CPU, const uint8_t amount, union xmm_reg *dst);
 void vec_shiftl_q128(NO_CPU, union xmm_reg *amount, union xmm_reg *dst);
 void vec_shiftr_q128(NO_CPU, union xmm_reg *amount, union xmm_reg *dst);
 void vec_add_b128(NO_CPU, union xmm_reg *src, union xmm_reg *dst);

diff --git a/tests/e2e/qemu/expected.txt b/tests/e2e/qemu/expected.txt
@@ -4430,6 +4430,10 @@ psllq    : a=231be9e8cde7438d007c62c2085427f8 ib=20 r=cde7438d00000000085427f800
 psllq    : a=007c62c2085427f8 ib=20 r=085427f800000000
 psllq    : a=dc515cff944a58ec456723c698694873 b=00000000000000000000000000000020 r=944a58ec000000009869487300000000
 psllq    : a=231be9e8cde7438d007c62c2085427f8 b=00000000000000000000000000000020 r=cde7438d00000000085427f800000000
+pslldq   : a=dc515cff944a58ec456723c698694873 ib=10 r=00000000000000000000000000000000
+pslldq   : a=231be9e8cde7438d007c62c2085427f8 ib=10 r=00000000000000000000000000000000
+pslldq   : a=dc515cff944a58ec456723c698694873 ib=07 r=ec456723c69869487300000000000000
+pslldq   : a=231be9e8cde7438d007c62c2085427f8 ib=07 r=8d007c62c2085427f800000000000000
 psrlq    : a=dc515cff944a58ec456723c698694873 ib=10 r=0000dc515cff944a0000456723c69869
 psrlq    : a=456723c698694873 ib=10 r=0000456723c69869
 psrlq    : a=231be9e8cde7438d007c62c2085427f8 ib=10 r=0000231be9e8cde70000007c62c20854

diff --git a/tests/e2e/qemu/qemu-test.c b/tests/e2e/qemu/qemu-test.c
@@ -2215,6 +2215,21 @@ static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
     }\
 }
 
+#define SHIFT_DQ_IM(op, ib)\
+{\
+    int i;\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    a.q[1] = test_values[2*i][1];\
+    asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           ib,\
+           r.q[1], r.q[0]);\
+    }\
+}
+
 #define SHIFT_OP(op, ib)\
 {\
     int i;\
@@ -2552,10 +2567,10 @@ void test_sse(void)
     SHIFT_OP(psllq, 7);
     SHIFT_OP(psllq, 32);
 
-    // SHIFT_IM(psrldq, 16);
-    // SHIFT_IM(psrldq, 7);
-    // SHIFT_IM(pslldq, 16);
-    // SHIFT_IM(pslldq, 7);
+    // SHIFT_DQ_IM(psrldq, 16);
+    // SHIFT_DQ_IM(psrldq, 7);
+    SHIFT_DQ_IM(pslldq, 16);
+    SHIFT_DQ_IM(pslldq, 7);
     SHIFT_IM(psrlq, 16);
     SHIFT_IM(psrlq, 7);
     SHIFT_IM(psllq, 16);