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Documentation Restructure (The-OpenROAD-Project#1337)
~ Documentation all moved under `docs/source`, arranged hierarchically according to the table of contents ~ `Klayout` changed to `KLayout` in all logging messages ~ Readme rewritten to just be concise, parts of it isolated into standalone documentation ~ RTD builds no longer use conda (saves some time) ~ Fixed all broken links
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| For more information about the OpenLane CI/CD, visit https://openlane.readthedocs.io/en/latest/for_developers/gha_workflow.html. |
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| # Additional Material | ||
| There are some cool tutorials and guides on using OpenLane to harden chips. Though do note, guides, especially video tutorials and webinars, tend to become out of date. | ||
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| Additionally, we're also going to link to academic publications about OpenLane if you're interested in reading and/or citing it. | ||
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| ## Text Guides | ||
| ### Official | ||
| - [OpenLane ReadTheDocs](https://openlane.readthedocs.io/) | ||
| - You're probably already here, though! Hi. | ||
| - [Quick-Start Guide, Caravel User Project ReadTheDocs](https://caravel-harness.readthedocs.io/en/latest/getting-started.html#quick-start-for-user-projects) | ||
| - If you're looking to submit a project for an OpenMPW or ChipIgnite shuttle, start here. | ||
| - [Digital inverter with OpenLane and Colab, Build Custom Silicon with Google](https://developers.google.com/silicon/guides/digital-inverter-openlane) | ||
| - This is a very simple introduction using Google Colab- you don't even need to install anything! | ||
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| ### Community | ||
| - [Introduction to OpenMPW, VLSI.jp](https://vlsi.jp/Introduction_to_OpenMPW.html#introduction-to-openmpw) | ||
| - [OpenMPW入門 改訂版, VLSI.jp](https://vlsi.jp/OpenMPW.html) | ||
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| ## Videos | ||
| - [Aboard Caravel, Ahmed Ghazy](https://www.youtube.com/watch?v=9QV8SDelURk) | ||
| - [FOSSi Dial-Up - Skywater PDK: Fully open source manufacturable PDK for a 130nm process, Tim Ansell](https://www.youtube.com/watch?v=EczW2IWdnOM&) | ||
| - [FOSSi Dial-Up - OpenLane, A Digital ASIC Flow for SkyWater 130nm Open PDK, Mohamed Shalan](https://www.youtube.com/watch?v=Vhyv0eq_mLU) | ||
| - [OpenLane Overview, Ahmed Ghazy](https://www.youtube.com/watch?v=d0hPdkYg5QI) | ||
| - [Free VLSI Tutorial - VSD - A complete guide to install OpenLane and Sky130nm PDK](https://www.udemy.com/course/vsd-a-complete-guide-to-install-openlane-and-sky130nm-pdk) | ||
| - [Sky130 - Exploring OpenLane and OpenDB to create a register file, Sylvain Munaut](https://www.youtube.com/watch?v=AT_LcmaCZmw) | ||
| - [Skywater 130nm PDK - Initial Discovery, Sylvain Munaut](https://www.youtube.com/watch?v=gRYBdTXbxiU) | ||
| - [VLSI SoC EDA OpenLane with Skywater 130 PDK, Gary Huang](https://www.youtube.com/watch?v=QnJzoJjC7RQ) | ||
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| ## Publications | ||
| This is a list of publications about OpenLane, sorted from newest to oldest. | ||
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| - R. Timothy Edwards, M. Shalan and M. Kassem, "Real Silicon using Open Source EDA," in IEEE Design & Test, doi: 10.1109/MDAT.2021.3050000. [Paper](https://ieeexplore.ieee.org/document/9336682) | ||
| - M. Shalan and T. Edwards, "Building OpenLANE: A 130nm OpenROAD-based Tapeout-Proven Flow: Invited Paper," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-6. [Paper](https://ieeexplore.ieee.org/document/9256623/) | ||
| - Ahmed Ghazy and Mohamed Shalan, "OpenLANE: The Open-Source Digital ASIC Implementation Flow", Article No.21, Workshop on Open-Source EDA Technology (WOSET), 2020. [Paper](https://github.com/woset-workshop/woset-workshop.github.io/blob/master/PDFs/2020/a21.pdf) |
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| ../../AUTHORS.md |
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| # OpenLane Architecture | ||
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| ## OpenLane Design Stages | ||
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| OpenLane flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLane can also be run interactively as shown [here][25]. | ||
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| 1. **Synthesis** | ||
| 1. `yosys/abc` - Perform RTL synthesis and technology mapping. | ||
| 2. `OpenSTA` - Performs static timing analysis on the resulting netlist to generate timing reports | ||
| 2. **Floorplaning** | ||
| 1. `init_fp` - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing) | ||
| 2. `ioplacer` - Places the macro input and output ports | ||
| 3. `pdngen` - Generates the power distribution network | ||
| 4. `tapcell` - Inserts welltap and decap cells in the floorplan | ||
| 3. **Placement** | ||
| 1. `RePLace` - Performs global placement | ||
| 2. `Resizer` - Performs optional optimizations on the design | ||
| 3. `OpenDP` - Perfroms detailed placement to legalize the globally placed components | ||
| 4. **CTS** | ||
| 1. `TritonCTS` - Synthesizes the clock distribution network (the clock tree) | ||
| 5. **Routing** | ||
| 1. `FastRoute` - Performs global routing to generate a guide file for the detailed router | ||
| 2. `TritonRoute` - Performs detailed routing | ||
| 3. `OpenRCX` - Performs SPEF extraction | ||
| 6. **Tapeout** | ||
| 1. `Magic` - Streams out the final GDSII layout file from the routed def | ||
| 2. `KLayout` - Streams out the final GDSII layout file from the routed def as a back-up | ||
| 7. **Signoff** | ||
| 1. `Magic` - Performs DRC Checks & Antenna Checks | ||
| 2. `KLayout` - Performs DRC Checks | ||
| 3. `Netgen` - Performs LVS Checks | ||
| 4. `CVC` - Performs Circuit Validity Checks | ||
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| OpenLane integrated several key open source tools over the execution stages: | ||
| - RTL Synthesis, Technology Mapping, and Formal Verification : [yosys + abc][4] | ||
| - Static Timing Analysis: [OpenSTA][8] | ||
| - Floor Planning: [init_fp][5], [ioPlacer][6], [pdn][16] and [tapcell][7] | ||
| - Placement: [RePLace][9] (Global), [Resizer][15] and [OpenPhySyn][28] (formerly), and [OpenDP][10] (Detailed) | ||
| - Clock Tree Synthesis: [TritonCTS][11] | ||
| - Fill Insertion: [OpenDP/filler_placement][10] | ||
| - Routing: [FastRoute][12] or [CU-GR][36] (formerly) and [TritonRoute][13] (Detailed) or [DR-CU][36] | ||
| - SPEF Extraction: [OpenRCX][37] or [SPEF-Extractor][27] (formerly) | ||
| - GDSII Streaming out: [Magic][14] and [KLayout][35] | ||
| - DRC Checks: [Magic][14] and [KLayout][35] | ||
| - LVS check: [Netgen][22] | ||
| - Antenna Checks: [Magic][14] | ||
| - Circuit Validity Checker: [CVC][31] | ||
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| > Everything in Floorplanning through Routing is done using [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) and its various sub-utilities. | ||
| ## OpenLane Output | ||
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| All output run data is placed by default under ./designs/design_name/runs. Each flow cycle will output a timestamp-marked folder containing the following file structure: | ||
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| ``` | ||
| <design_name> | ||
| ├── config.json/config.tcl | ||
| ├── runs | ||
| │ ├── <tag> | ||
| │ │ ├── config.tcl | ||
| │ │ ├── {logs, reports, tmp} | ||
| │ │ │ ├── cts | ||
| │ │ │ ├── signoff | ||
| │ │ │ ├── floorplan | ||
| │ │ │ ├── placement | ||
| │ │ │ ├── routing | ||
| │ │ │ └── synthesis | ||
| │ │ ├── results | ||
| │ │ │ ├── final | ||
| │ │ │ ├── cts | ||
| │ │ │ ├── signoff | ||
| │ │ │ ├── floorplan | ||
| │ │ │ ├── placement | ||
| │ │ │ ├── routing | ||
| │ │ │ └── synthesis | ||
| ``` | ||
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| To delete all generated runs under all designs: | ||
| `make clean_runs` | ||
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| [1]: ../for_developers/docker.md | ||
| [4]: https://github.com/YosysHQ/yosys | ||
| [5]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ifp | ||
| [6]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ppl | ||
| [7]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/tap | ||
| [8]: https://github.com/The-OpenROAD-Project/OpenSTA | ||
| [9]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/replace | ||
| [10]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/dpl | ||
| [11]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/cts | ||
| [12]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/grt | ||
| [13]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/TritonRoute | ||
| [14]: https://github.com/RTimothyEdwards/magic | ||
| [15]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rsz | ||
| [16]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pdn | ||
| [18]: https://github.com/RTimothyEdwards/qflow/blob/master/src/addspacers.c | ||
| [19]: https://github.com/The-OpenROAD-Project/ | ||
| [20]: https://github.com/git-lfs/git-lfs/wiki/Installation | ||
| [21]: /usage/exploration_script.md | ||
| [22]: https://github.com/RTimothyEdwards/netgen | ||
| [24]: ./for_developers/pdk_structure.md | ||
| [25]: ./reference/interactive_mode.md | ||
| [26]: ./usage/chip_integration.md | ||
| [27]: https://github.com/AUCOHL/spef-extractor | ||
| [28]: https://github.com/scale-lab/OpenPhySyn | ||
| [29]: ./usage/hardening_macros.md | ||
| [30]: ./usage/building_the_pdk.md | ||
| [31]: https://github.com/d-m-bailey/cvc | ||
| [32]: ./for_developers/code_contribution.md | ||
| [33]: ./authors.md | ||
| [34]: ./reference/openlane_commands.md | ||
| [35]: https://github.com/KLayout/klayout | ||
| [36]: https://github.com/cuhk-eda/cu-gr | ||
| [37]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rcx | ||
| [38]: ./for_developers/issue_regression_tests.md | ||
| [39]: https://github.com/cuhk-eda/dr-cu |
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| ../../../CONTRIBUTING.md |
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| ../../../docker/README.md |
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