Python Cleanup (The-OpenROAD-Project#864)

+ Consolidated all existing DRC conversion functions into `drc_rosetta.py` + Consolidated fake_diode_replace and place_diode into `diode.py` + Consolidated and/or rewrote most def manipulation functions into `defutil.py` and other files under `odbpy/`. + Consolidated and/or rewrote most lef manipulation functions into `lefutil.py` ~ Moved all files using odb to a new folder, `odbpy/` ~ Move replicate/update config scripts to `scripts/config` folder ~ Move all in-line magic spells into proper files ~ Tcl formatting (4 space-indents on all modified files) - Removed many unused files, all consolidated files --- API Breaks * Care was taken to ensure all OpenLane tcl commands have the same API presuming the API in question was not stupid. * Speaking of, `manual_macro_placement_test f` has been updated to `manual_macro_placement_test -f` to be consistent with literally every other command. * All individual files that may be used by third party projects likely have a different CLI and are thus entirely broken.
MrShaTr · Jun 7, 2022 · b29b715 · b29b715
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diff --git a/configuration/README.md b/configuration/README.md
@@ -312,8 +312,8 @@ These variables worked initially, but they were too sky130 specific and will be
 | `USE_ARC_ANTENNA_CHECK` | Specifies whether to use the openroad ARC antenna checker or magic antenna checker. 0=magic antenna checker, 1=ARC OR antenna checker <br> (Default: `1`)
 | `RUN_SPEF_EXTRACTION` | Specifies whether or not to run SPEF extraction on the routed DEF. 1=enabled 0=disabled <br> Default: `1` |
 | `GENERATE_FINAL_SUMMARY_REPORT` | Specifies whether or not to generate a final summary report after the run is completed. Check command `generate_final_summary_report`. 1=enabled 0=disabled <br> Default: `1` |
-| `MAGIC_CONVERT_DRC_TO_RDB` | Specifies whether or not generate a Calibre RDB out of the magic.drc report. Result is saved in `<run_path>/results/magic/`. 1=enabled 0=disabled <br> Default: `1`|
 | `RUN_CVC` | Runs CVC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. Thus, it controls the command `run_lef_cvc`. 1=Enabled, 0=Disabled. <br> Default: `1` |
+| `MAGIC_CONVERT_DRC_TO_RDB` | **Removed: Will always run** Specifies whether or not generate a Calibre RDB out of the magic.drc report. Result is saved in `<run_path>/results/magic/`. 1=enabled 0=disabled <br> Default: `1`|
 
 ### Checkers
 

diff --git a/designs/README.md b/designs/README.md
@@ -87,12 +87,12 @@ Two scripts were created for this purpose:
 
 To run the script to create new (empty) configurations for a (PDK,STD_CELL_LIBRARY) pair:
 ```bash
-    python3 ./scripts/replicate_design_configs.py --to-pdk PDK --to-std-cell-lib STD_CELL_LIBRARY
+    python3 ./scripts/config/replicate.py --to-pdk PDK --to-std-cell-lib STD_CELL_LIBRARY
 ```
 
 To run the script to replicate configurations from one (PDK,STD_CELL_LIBRARY) pair to another:
 ```bash
-    python3 ./scripts/replicate_design_configs.py --from-pdk PDK_FROM --from-std-cell-lib STD_CELL_LIBRARY_FROM --to-pdk PDK --to-std-cell-lib STD_CELL_LIBRARY
+    python3 ./scripts/config/replicate.py --from-pdk PDK_FROM --from-std-cell-lib STD_CELL_LIBRARY_FROM --to-pdk PDK --to-std-cell-lib STD_CELL_LIBRARY
 ```
 
 The following is the list of flags used with the script:
@@ -153,7 +153,7 @@ The following is the list of flags used with the script:
 
 To run the script to update configurations for a (PDK,STD_CELL_LIBRARY) pair after an exploration:
 ```bash
-    python3 ./scripts/update_designs_configs.py --pdk PDK --std-cell-lib STD_CELL_LIBRARY --best_results SW_exploration_best.csv
+    python3 ./scripts/config/update.py --pdk PDK --std-cell-lib STD_CELL_LIBRARY --best_results SW_exploration_best.csv
 ```
 
 Check [this][1] for more details on the log files.
@@ -233,9 +233,9 @@ The following is the list of flags used with the script:
     </tr>
 </table>
 
-**Note:** `update_designs_configs.py` skips designs that fail during the exploration, which means their flow_status is not `flow_completed`.
+**Note:** `config/update.py` skips designs that fail during the exploration, which means their flow_status is not `flow_completed`.
 
-**Important Note:** *The `update_designs_configs` script only copies new configuration to the file. The new configurations are marked with a preceeding "# Regression" comment that is automatically written before them by the exploration script. However, the `replicate_design_configs` script copies the whole file.*
+**Important Note:** *The `update.py` script only copies new configuration to the file. The new configurations are marked with a preceeding "# Regression" comment that is automatically written before them by the exploration script. However, the `replicate.py` script copies the whole file.*
 
 [1]: ../regression_results/README.md
 [2]: ../configuration/README.md
diff --git a/docs/source/chip_integration.md b/docs/source/chip_integration.md
@@ -79,7 +79,7 @@ The following inputs are provided to produce the final GDSII:
 - Sources configurations.
 - Elaborates the verilog.
 - Runs floorplan.
-- Uses padringer.py to generate the padframe.
+- Uses odbpy/padringer.py to generate the padframe.
 - Adds the obstructions to the core area, and removes core nets and pins.
 - Routes.
 - Streams out the GDS-II and the LEFv view.

diff --git a/docs/source/openlane_commands.md b/docs/source/openlane_commands.md
@@ -60,7 +60,7 @@ Most of the following commands' implementation exists in this [file][0]
 |    | `-netlist_def <def_file>` |  DEF view of the design that has the connectivity information.|
 |    | `-pad_pin_name <pad_pin_name>` |  Name of the pin of the pad as it appears in the netlist def. |
 |    | `[-output <output_def>]` |  Output labeled def file. <br> Defaults to the `CURRENT_DEF`. <br> Optional flag.|
-|    | `[-extra_args <extra_args>]` | Gives extra control on the rest of the flags of the labeling script. For more information on the other args that the script supports, run: `python3 $OPENLANE_ROOT/scripts/label_macro_pins.py -h`. <br> Optional flag.|
+|    | `[-extra_args <extra_args>]` | Gives extra control on the rest of the flags of the labeling script. For more information on the other args that the script supports, run: `openroad -python $OPENLANE_ROOT/scripts/odbpy/label_macro_pins.py -h`. <br> Optional flag.|
 | `write_verilog <filename>` | | Generates a verilog netlist from a given def file. Stores the resulting netlist in `<filename>`, and sets the generated netlist as the `CURRENT_NETLIST` used by the flow.|
 |    | `[-def <def_file>]` |  DEF view of the design from which to generate the netlist. <br> Defaults to the `CURRENT_DEF`. <br> Optional flag.|
 | `add_macro_obs` | |Creates and obstruction in def and lef files.|
@@ -79,9 +79,7 @@ Most of the following commands' implementation exists in this [file][0]
 |    | `-layer <layer_name>` | layer to change.|
 |    | `-valuesFile <file>` |  tmp file to read the new track values from.|
 |    | `-originalFile <file>` |  tmp file to store the original value.|
-| `padframe_extract_area` | | Returns the Diearea extracted from the given padframe configuration file. |
-|    | `-cfg <padframe_configurations_file>` | The file containing the padframe information. |
-| `set_core_dims` | | Extracts the core dimensions based on the existing set environment variables. The results are set into `CORE_WIDTH` and `CORE_HEIGHT`. |
+| `extract_core_dims` | | Extracts the core dimensions based on the existing set environment variables. The results are set into `CORE_WIDTH` and `CORE_HEIGHT`. |
 |    | `-log_path <path>` | The path to write the logs into. |
 | `run_spef_extraction` | | Runs SPEF extraction on the `::env(CURRENT_DEF)` file followed by Static Timing Analysis using OpenSTA. The results are reported under `<run_path>/reports/<step>/opensta_spef_*`. |
 | `run_antenna_check` | | Runs antenna checks based on the value of `::env(USE_ARC_ANTENNA_CHECK)` either calling `run_or_antenna_check` or `run_magic_antenna_check`. |
@@ -182,7 +180,7 @@ Most of the following commands' implementation exists in this [file][7]
 | `detailed_placement_or` | | Runs detailed placement on the processed design using OpenROAD. The resulting file is under `/<run_path>/results/placement/` . |
 | `detailed_placement` | | Alias for `detailed_placement_or`. |
 | `add_macro_placement <macro_name> <x_coordinate> <y_coordinate> [<orientation>]` | | Writes a configuration file to be processed by `manual_macro_placement` by setting the initial placement of the macro `<macro_name>` to location (`<x_coordinate>`,`<y_coordinate>`) on the chip with the option of specifying the `<orientation>` as well. The line written will be appened to this configuration file `/run_path/tmp/macro_placements.cfg`. |
-| `manual_macro_placement [f]` | | Uses the configuration file generated by `add_macro_placement` (`/run_path/tmp/macro_placements.cfg`) to manually initialize the placement of the macros to the locations determined in the file. It works on the currently processed design and it overwrites the `CURRENT_DEF`. if `f` is passed as the first argument, the placement will be fixed and final, and the placement tools will not be allowed to change it.|
+| `manual_macro_placement [-f]` | | Uses the configuration file generated by `add_macro_placement` (`/run_path/tmp/macro_placements.cfg`) to manually initialize the placement of the macros to the locations determined in the file. It works on the currently processed design and it overwrites the `CURRENT_DEF`. if `-f` is passed as an argument, the placement will be fixed and final, and the placement tools will not be allowed to change it.|
 | `basic_macro_placement` | | Runs basic macro placement on the chip level using the openroad app, and it writes into `::env(CURRENT_DEF).macro_placement.def`. |
 | `run_resizer_design` | | Runs resizer design optimizations to insert buffers on nets to repair max slew, max capacitance, max fanout violations, and on long wires to reduce RC delay in the wire. It also resizes cells. |
 | `run_placement`| | Runs global placement (`global_placement_or` or `random_global_placement` based on the value of `PL_RANDOM_GLB_PLACEMENT`), then applies the optional optimizations `repair_wire_length` followed by `run_openPhySyn` if enabled, then runs the detailed placement (`detailed_placement_or`). |