Enhancements to variables related to SDC files (The-OpenROAD-Project#…

…1931) + Warn when IMPLEMENTATION_SDC_FILE is not overwritten by the user. + Add SDC_IN and IMPLEMENTATION_SDC_FILE_DEFAULT to ignore list in ci Check Variables flow ~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE. ~ Rename BASE_SDC_FILE to IMPLEMENTATION_SDC_FILE. ~ Always use IMPLMEMENTATION_SDC_FILE instead of CURRENT_SDC except during signoff stage
MrShaTr · Aug 10, 2023 · 7a5857a · 7a5857a
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diff --git a/.github/scripts/variables_documentation.py b/.github/scripts/variables_documentation.py
@@ -48,6 +48,7 @@
 GRT_CONGESTION_REPORT_FILE
 INSERT_BUFFER_COMMAND
 INSERT_BUFFER_COUNTER
+IMPLEMENTATION_SDC_FILE_DEFAULT
 IO_READ_DEF
 LAST_TIMING_REPORT_TAG
 LEC_LHS_NETLIST
@@ -89,6 +90,7 @@
 SAVE_SPEF
 SCRIPTS_DIR
 SCRIPT_DIR
+SDC_IN
 START_TIME
 STA_MULTICORNER
 STA_PRE_CTS

diff --git a/configuration/synthesis.tcl b/configuration/synthesis.tcl
@@ -33,5 +33,6 @@ set ::env(SYNTH_FLAT_TOP) 0
 set ::env(IO_PCT) 0.2
 set ::env(SYNTH_EXTRA_MAPPING_FILE) ""
 
-set ::env(BASE_SDC_FILE) $::env(SCRIPTS_DIR)/base.sdc
+set ::env(IMPLEMENTATION_SDC_FILE) $::env(SCRIPTS_DIR)/base.sdc
+set ::env(IMPLEMENTATION_SDC_FILE_DEFAULT) $::env(SCRIPTS_DIR)/base.sdc
 
diff --git a/designs/ci b/designs/ci
diff --git a/docs/source/reference/configuration.md b/docs/source/reference/configuration.md
@@ -40,6 +40,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | `MERGED_LEF` <a id="MERGED_LEF"></a> | Points to `merged.lef`, which is a merger of various LEF files, including the technology lef, cells lef, any custom lefs, and IO lefs. |
 | `NO_SYNTH_CELL_LIST` <a id="NO_SYNTH_CELL_LIST"></a> | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
 | `DRC_EXCLUDE_CELL_LIST` <a id="DRC_EXCLUDE_CELL_LIST"></a> | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells` and if it's not found, then the original liberty will be used as is. In other words, `DRC_EXCLUDE_CELL_LIST` contain the only excluded cell list in timing optimizations. |
+| `IMPLEMENTATION_SDC_FILE` <a id="IMPLEMENTATION_SDC_FILE"></a> | Specifies the sdc file used during all implementation stages (synthesis, optimizations, CTS, etc.) in the flow and during sta done at these stages. It is *not* used during signoff stage. <br> (Default: `$::env(OPENLANE_ROOT)/scripts/base.sdc`) |
 
 ### Macros/Chip Integration
 
@@ -90,7 +91,6 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | `SYNTH_EXTRA_MAPPING_FILE` <a id="SYNTH_EXTRA_MAPPING_FILE"></a> | Points to extra techmap file for yosys that runs right after yosys `synth` before generic techmap. <br> (Default: `""`)|
 | `SYNTH_PARAMETERS` <a id="SYNTH_PARAMETERS"></a> | Whitespace-delimited key value pairs to be `chparam`ed in Yosys. In the format `key1=value1 key2=value2` <br> (Default: None)  |
 | `SYNTH_ELABORATE_ONLY` <a id="SYNTH_ELABORATE_ONLY"></a> | "Elaborate" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. <br> (Default: `0`) |
-| `BASE_SDC_FILE` <a id="BASE_SDC_FILE"></a> | Specifies the base sdc file to source before running Static Timing Analysis. <br> (Default: `$::env(OPENLANE_ROOT)/scripts/base.sdc`) |
 | `VERILOG_INCLUDE_DIRS` <a id="VERILOG_INCLUDE_DIRS"></a> | Specifies the verilog includes directories. <br> Optional. |
 | `SYNTH_FLAT_TOP` <a id="SYNTH_FLAT_TOP"></a> | Specifies whether or not the top level should be flattened during elaboration. 1 = True, 0= False <br> (Default: `0`)|
 | `IO_PCT` <a id="IO_PCT"></a> | Specifies the percentage of the clock period used in the input/output delays. Ranges from 0 to 1.0. <br> (Default: `0.2`) |
@@ -99,6 +99,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | `SYNTH_TOP_LEVEL` <a id="SYNTH_TOP_LEVEL"></a> | **Deprecated: Use `SYNTH_ELABORATE_ONLY`**: "Elaborate" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. |
 | `SYNTH_MAX_FANOUT` <a id="SYNTH_MAX_FANOUT"></a>  | **Deprecated: Use the PDK's `MAX_FANOUT_CONSTRAINT` value**: The max load that the output ports can drive. |
 | `SYNTH_MAX_TRAN` <a id="SYNTH_MAX_TRAN"></a> |  **Deprecated: Use the PDK's `MAX_TRANSITION_CONSTRAINT` value**: The max transition time (slew) from high to low or low to high on cell inputs in ns. If unset, the library's default maximum transition time will be used. |
+| `BASE_SDC_FILE` <a id="BASE_SDC_FILE"></a> | **Deprecated: Use IMPLEMENTATION_SDC_FILE**: Specifies the base sdc file to source before running Static Timing Analysis. <br> (Default: `$::env(OPENLANE_ROOT)/scripts/base.sdc`) |
 
 ## Static Timing Analysis (STA)
 
@@ -303,7 +304,7 @@ These variables worked initially, but they were too sky130 specific and will be
 | `RUN_SPEF_EXTRACTION` <a id="RUN_SPEF_EXTRACTION"></a> | Specifies whether or not to run SPEF extraction on the routed DEF. 1=enabled 0=disabled <br> (Default: `1`) |
 | `SPEF_EXTRACTOR` <a id="SPEF_EXTRACTOR"></a> | Specifies which spef extractor to use. Values: `openrcx` or (**removed:** `def2spef`). <br> (Default: `openrcx`) |
 | `RCX_MERGE_VIA_WIRE_RES` <a id="RCX_MERGE_VIA_WIRE_RES"></a> | Specifies whether to merge the via resistance with the wire resistance or separate it from the wire resistance. 1 = Merge via resistance, 0 = Separate via resistance <br> (Default: `1`)|
-| `RCX_SDC_FILE` <a id="RCX_SDC_FILE"></a> | Specifies SDC file to be used for RCX-based STA, which can be different from the one used for implementation. <br> (Default: `BASE_SDC_FILE`) |
+| `RCX_SDC_FILE` <a id="RCX_SDC_FILE"></a> | **Deprecated: Use SIGNOFF_SDC_FILE.**: Specifies SDC file to be used for RCX-based STA, which can be different from the one used for implementation. <br> (Default: `BASE_SDC_FILE`) |
 | `SPEF_WIRE_MODEL` <a id="SPEF_WIRE_MODEL"></a> | **Removed:** Specifies the wire model used in SPEF extraction. Options are `L` or `Pi` |
 | `SPEF_EDGE_CAP_FACTOR` <a id="SPEF_EDGE_CAP_FACTOR"></a> | **Removed:** Specifies the edge capacitance factor used in SPEF extraction. Ranges from 0 to 1 |
 
@@ -322,6 +323,7 @@ These variables worked initially, but they were too sky130 specific and will be
 | `PRIMARY_SIGNOFF_TOOL` <a id="PRIMARY_SIGNOFF_TOOL"></a> | Determines whether `magic` or `klayout` is the primary signoff tool. <br> (Default: `magic`) |
 | `USE_ARC_ANTENNA_CHECK` <a id="USE_ARC_ANTENNA_CHECK"></a> | Specifies whether to use the openroad ARC antenna checker or magic antenna checker. 0=magic antenna checker, 1=ARC OR antenna checker <br> (Default: `1`)
 | `RUN_CVC` <a id="RUN_CVC"></a> | Runs CVC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `SIGNOFF_SDC_FILE` <a id="SIGNOFF_SDC_FILE"></a> | Specifies SDC file to be used for multicorner STA during signoff stage, which can be different from the one used for implementation. <br> (Default: `IMPLEMENTATION_SDC_FILE`) |
 
 ### Magic
 |Variable|Description|

diff --git a/docs/source/usage/hardening_macros.md b/docs/source/usage/hardening_macros.md
@@ -72,7 +72,7 @@ Static Timing Analysis happens multiple times during the flow. However, they all
 
 3. The IO delay percentage from the clock period `IO_PCT`. More about that [here](../reference/configuration.md).
 
-4. You may want to write a custom SDC file to be used in STA and CTS. The default SDC file in the flow is as follows. However, you can change that by pointing to a new file with the environment variable `BASE_SDC_FILE`. More about that [here](../reference/configuration.md).
+4. You may want to write a custom SDC file to be used in STA and CTS. The default SDC file in the flow is as follows. However, you can change that by pointing to a new file with the environment variable `IMPLEMENTATION_SDC_FILE`. More about that [here](../reference/configuration.md).
 
 Other values are set based on the (PDK, STD_CELL_LIBRARY) used. You can read more about those configurations [here](../reference/configuration.md).
 

diff --git a/scripts/openroad/common/io.tcl b/scripts/openroad/common/io.tcl
@@ -35,8 +35,8 @@ proc env_var_used {file var} {
 }
 
 proc read_current_sdc {} {
-    if { ![info exists ::env(CURRENT_SDC)]} {
-        puts "\[INFO] CURRENT_SDC not found. Not reading an SDC file."
+    if { ![info exists ::env(SDC_IN)]} {
+        puts "\[INFO] SDC_IN not found. Not reading an SDC file."
         return
     }
 
@@ -46,8 +46,8 @@ proc read_current_sdc {} {
         set ::env(SYNTH_MAX_TRAN) $::env(MAX_TRANSITION_CONSTRAINT)
     }
 
-    puts "Reading design constraints file at '$::env(CURRENT_SDC)'…"
-    if {[catch {read_sdc $::env(CURRENT_SDC)} errmsg]} {
+    puts "Reading design constraints file at '$::env(SDC_IN)'…"
+    if {[catch {read_sdc $::env(SDC_IN)} errmsg]} {
         puts stderr $errmsg
         exit 1
     }
@@ -90,9 +90,7 @@ proc read_netlist {args} {
 
     link_design $::env(DESIGN_NAME)
 
-    if { [info exists ::env(CURRENT_SDC)] } {
-        read_current_sdc
-    }
+    read_current_sdc
 
 }
 
@@ -188,9 +186,7 @@ proc read {args} {
 
     read_libs {*}$read_libs_args
 
-    if { [info exists ::env(CURRENT_SDC)] } {
-        read_current_sdc
-    }
+    read_current_sdc
 
     if { ![info exist flags(-no_spefs)] } {
         if { [info exists ::env(CURRENT_SPEF)] } {

diff --git a/scripts/tcl_commands/all.tcl b/scripts/tcl_commands/all.tcl
@@ -635,6 +635,9 @@ proc prep {args} {
     handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB
     handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX
 
+    handle_deprecated_config RCX_SDC_FILE SIGNOFF_SDC_FILE
+    handle_deprecated_config BASE_SDC_FILE IMPLEMENTATION_SDC_FILE
+
     ### Checkers/Quitting
     handle_deprecated_config CHECK_ASSIGN_STATEMENTS QUIT_ON_ASSIGN_STATEMENTS
     handle_deprecated_config CHECK_UNMAPPED_CELLS QUIT_ON_UNMAPPED_CELLS
@@ -905,6 +908,10 @@ proc prep {args} {
         }
     }
 
+    if { $::env(IMPLEMENTATION_SDC_FILE) == $::env(IMPLEMENTATION_SDC_FILE_DEFAULT) } {
+        puts_warn "Using default sdc file $::env(IMPLEMENTATION_SDC_FILE). It is recommended to provide a custom sdc file made by the designer."
+    }
+
     TIMER::timer_stop
     exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "openlane design prep"
     return -code ok

diff --git a/scripts/tcl_commands/sta.tcl b/scripts/tcl_commands/sta.tcl
@@ -124,12 +124,13 @@ proc run_parasitics_sta {args} {
     # * CURRENT_SPEF is the nom SPEF after the loop is done
     # * CURRENT_LIB is the nom/nom LIB after the loop is done
     # * CURRENT_SDF is the nom/nom SDF after the loop is done
-    if { ![info exists ::env(RCX_SDC_FILE)] } {
-        set ::env(RCX_SDC_FILE) $::env(CURRENT_SDC)
+    if { ![info exists ::env(SIGNOFF_SDC_FILE)] } {
+        set ::env(SIGNOFF_SDC_FILE) $::env(CURRENT_SDC)
+        set ::env(SIGNOFF_SDC_FILE) $::env(SDC_IN)
     }
 
     set backup_sdc_variable $::env(CURRENT_SDC)
-    set ::env(CURRENT_SDC) $::env(RCX_SDC_FILE)
+    set ::env(CURRENT_SDC) $::env(SIGNOFF_SDC_FILE)
 
     set mca_results_dir "$arg_values(-out_directory)/mca"
     set ::env(MC_SPEF_DIR) "$mca_results_dir/spef"
@@ -147,6 +148,7 @@ proc run_parasitics_sta {args} {
             set directory "$mca_results_dir/process_corner_$process_corner"
             file mkdir $directory
 
+            # Note that sdc used here is different than the rest of the flow. The question is whether this would impact rcx extraction or not.
             run_spef_extraction\
                 -log $::env(signoff_logs)/parasitics_extraction.$process_corner.log\
                 -rcx_lib $::env(LIB_SYNTH_COMPLETE)\

diff --git a/scripts/tcl_commands/synthesis.tcl b/scripts/tcl_commands/synthesis.tcl
@@ -112,7 +112,8 @@ proc run_synthesis {args} {
     set log [index_file $::env(synthesis_logs)/synthesis.log]
     puts_info "Running Synthesis (log: [relpath . $log])..."
 
-    set ::env(CURRENT_SDC) $::env(BASE_SDC_FILE)
+    set ::env(CURRENT_SDC) $::env(IMPLEMENTATION_SDC_FILE)
+    set ::env(SDC_IN) $::env(IMPLEMENTATION_SDC_FILE)
     # in-place insertion
     if { [file exists $::env(synthesis_results)/$::env(DESIGN_NAME).v] } {
         puts_warn "A netlist at $::env(synthesis_results)/$::env(DESIGN_NAME).v already exists. Synthesis will be skipped."

diff --git a/scripts/utils/utils.tcl b/scripts/utils/utils.tcl
@@ -383,7 +383,7 @@ proc show_warnings {msg} {
         set warnings_file [open $::env(RUN_DIR)/warnings.log "r"]
         set warnings [read $warnings_file]
         close $warnings_file
-        puts $warnings
+        puts "[color_text 3 "$warnings"]"
     }
 }
+4 −1		APU/config.json
+2 −0		caravel_upw/config.tcl
+6 −0		caravel_upw/src/user_proj_example.v
+4 −0		caravel_upw/src/user_proj_example2.v