Fix Netlist STA Reproducible + Update Docs (The-OpenROAD-Project#1610)

+ Update reproducible uploading docs + Documented a number of missing configuration variables ~ Fix an issue where netlist STA reproducibles would attempt to use `CURRENT_ODB` and crash - Removed a number of unused configuration variables
MrShaTr · Jan 11, 2023 · 06b2681 · 06b2681
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diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -42,10 +42,12 @@ body:
         ---
         You also need to upload some files so we can reproduce your issue.
 
-        1. If you see a message like `Reproducible packaged: Please tarball and upload <PATH> if you're going to submit an issue` in your logs,  please compress and upload that folder by dragging the .tar.gz or the .zip file to the following text field. The reproducible tarball is 100% required for OpenROAD bugs.
+        1. If you see a message like `Reproducible packaged: Please tarball and upload <PATH> if you're going to submit an issue` in your logs,  please compress and upload that folder by dragging the .tar.gz or the .zip file to the following text field.
+        * The reproducible tarball is 100% required for OpenROAD bugs.
+        * If the file is too large, you may split the upload over multiple .zip or .tar.gz files.
 
         2. If you don't...
-            * Please compress and upload that folder by dragging the .tar.gz or the .zip file to the following text field.
+            * Please compress and upload the design folder by dragging the .tar.gz or the .zip file to the following text field.
             * List the commands used to run the design.
   - type: textarea
     id: reproduction-material

diff --git a/docs/source/for_developers/pdk_structure.md b/docs/source/for_developers/pdk_structure.md
@@ -80,7 +80,6 @@ This section defines the necessary variables to configure a standard cell librar
 | `LIB_SLOWEST` | Points to the lib file, corresponding to the slowest corner, for max delay calculation during STA. |
 | `LIB_FASTEST` | Points to the lib file, corresponding to the fastest corner, for min delay calculation during STA. |
 | `LIB_TYPICAL` | Points to the lib file for typical delay calculation during STA. |
-| `NO_SYNTH_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
 | `PLACE_SITE` | Defines the main site used by the cells. Used during floorplanning to generate the rows. |
 | `PLACE_SITE_WIDTH` | Defines the main site width. Used during floorplanning to generate the rows. |
 | `PLACE_SITE_HEIGHT` | Defines the main site height. Used during floorplanning to generate the rows. |
@@ -94,21 +93,18 @@ This section defines the necessary variables to configure a standard cell librar
 | `SYNTH_MIN_BUF_PORT` | Defines the buffer, followed by its input port and output port to be used by `ins_buf` statements by yosys. It inserts buffer cells into the design for directly connected wires. <br> (Example: `sky130_fd_sc_hd__buf_2 A X`  )|
 | `SYNTH_TIEHI_PORT` | Defines the tie high cell followed by the port that implements the tie high functionality. Used in synthesis. <br> (Example: `sky130_fd_sc_hd__conb_1 HI`)|
 | `SYNTH_TIELO_PORT` | Defines the tie low cell followed by the port that implements the tie high functionality. Used in synthesis. <br> (Example: `sky130_fd_sc_hd__conb_1 LO`)|
-| `CELL_CLK_PORT` | Defines the name of clk port of the flip flops and other cells. Used in CTS. |
-| `PL_LIB` | Points to the lib view used in time driven placement.  |
 | `FILL_CELL` | Defines the fill cell. Used in fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
 | `DECAP_CELL` | Defines the decap cell used for fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
 | `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. Using this is not strictly recommended as you can simply use the density control for global placement. <br> (Example: `0`) |
 | `DPL_CELL_PADDING` | Defines the number of sites to pad the cells lef views with during detailed placement . The number will be integer divided by 2 and placed on both sides. <br> (Example: `4`) |
 | `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding for both detailed placement. |
 | `CTS_ROOT_BUFFER` | Defines the cell inserted at the root of the clock tree. Used in CTS. |
-| `ROOT_CLK_BUFFER` | Root clock buffer of the clock tree. <br> (Example: `sky130_fd_sc_hd__clkbuf_16`) |
-| `CLK_BUFFER` | Clock buffer used for inner nodes of the clock tree. <br> (Example: `sky130_fd_sc_hd__clkbuf_4`) |
-| `CLK_BUFFER_INPUT` | Input pin of the clock tree buffer. <br> (Example: `A`) |
-| `CLK_BUFFER_OUTPUT` | Output pin of the clock tree buffer. <br> (Example: `X`)|
 | `CTS_CLK_BUFFER_LIST` | Defines the list of clock buffers to be used in CTS. |
 | `CTS_MAX_CAP` | Defines the maximum capacitance, used in CTS. |
-| `FP_PDN_RAIL_WIDTH` | Defines the rail width for met1 used in PDN. |
+| `FP_PDN_UPPER_LAYER` | Defines the upper layer used in PDN. |
+| `FP_PDN_LOWER_LAYER` | Defines the lower layer used in PDN. |
+| `FP_PDN_RAILS_LAYER` | Defines the rail layer used in PDN. |
+| `FP_PDN_RAIL_WIDTH` | Defines the rail width for the rail layer used in PDN. |
 | `SYNTH_LATCH_MAP` | A pointer for the file contianing the latch mapping for yosys. |
 | `TRISTATE_BUFFER_MAP` | A pointer for the file containing the tri-state buffer mapping for yosys. |
 | `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |

diff --git a/docs/source/reference/configuration.md b/docs/source/reference/configuration.md
@@ -147,7 +147,6 @@ These variables worked initially, but they were too sky130 specific and will be
 |-|-|
 | `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `($::env(FP_CORE_UTIL) +5 ) / 100.0`)|
 | `PL_TIME_DRIVEN` | Specifies whether the placer should use time driven placement. 0 = false, 1 = true <br> (Default: `1`)|
-| `PL_LIB` | Specifies the library for time driven placement <br> (Default: `LIB_TYPICAL`)|
 | `PL_BASIC_PLACEMENT` | Specifies whether the placer should run basic placement. Basic placement is used for extremely simple, low-density designs of only a few dozens of gates, and should be disabled for most designs. 0 = false, 1 = true <br> (Default: `0`) |
 | `PL_SKIP_INITIAL_PLACEMENT` | Specifies whether the placer should run initial placement or not. 0 = false, 1 = true <br> (Default: `0`) |
 | `PL_RANDOM_GLB_PLACEMENT` | Specifies whether the placer should run random placement or not. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true <br> (Default: `0`) |

diff --git a/scripts/tcl_commands/sta.tcl b/scripts/tcl_commands/sta.tcl
@@ -13,6 +13,11 @@
 # limitations under the License.
 
 proc run_sta {args} {
+    if {![info exists ::env(CLOCK_PORT)]} {
+        puts_warn "CLOCK_PORT is not set. STA will be skipped..."
+        return
+    }
+
     set options {
         {-log required}
         {-process_corner optional}
@@ -21,6 +26,7 @@ proc run_sta {args} {
     set flags {
         -multi_corner
         -pre_cts
+        -netlist_in
     }
     parse_key_args "run_sta" args arg_values $options flags_map $flags
 
@@ -52,24 +58,24 @@ proc run_sta {args} {
         set lib_option "lib"
     }
 
-    if {[info exists ::env(CLOCK_PORT)]} {
-        if { $multi_corner == 1 } {
-            run_openroad_script $::env(SCRIPTS_DIR)/openroad/sta_multi_corner.tcl \
-                -indexed_log $log\
-                -save "to=$arg_values(-save_to),noindex,sdf,$lib_option"\
-                -no_update_current
+    set arg_list [list]
+    lappend arg_list -indexed_log $log
+    lappend arg_list -save "to=$arg_values(-save_to),noindex,sdf,$lib_option"
+    if { [info exists flags_map(-netlist_in)] } {
+        lappend arg_list -netlist_in
+    }
 
-            if { $::env(STA_WRITE_LIB) } {
-                unset ::env(SAVE_LIB)
-            }
-            unset ::env(SAVE_SDF)
-        } else {
-            run_openroad_script $::env(SCRIPTS_DIR)/openroad/sta.tcl \
-                -indexed_log $log\
-                -save "to=$arg_values(-save_to),noindex,sdf,$lib_option"
+    if { $multi_corner == 1 } {
+        run_openroad_script $::env(SCRIPTS_DIR)/openroad/sta_multi_corner.tcl \
+            -no_update_current\
+            {*}$arg_list
+
+        if { $::env(STA_WRITE_LIB) } {
+            unset ::env(SAVE_LIB)
         }
+        unset ::env(SAVE_SDF)
     } else {
-        puts_warn "CLOCK_PORT is not set. STA will be skipped..."
+        run_openroad_script $::env(SCRIPTS_DIR)/openroad/sta.tcl {*}$arg_list
     }
     TIMER::timer_stop
     exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "sta - openroad"

diff --git a/scripts/tcl_commands/synthesis.tcl b/scripts/tcl_commands/synthesis.tcl
@@ -66,8 +66,8 @@ proc run_yosys {args} {
         set_netlist -lec $::env(SAVE_NETLIST)
     }
 
-        # The following is a naive workaround to OpenROAD not accepting defparams.
-        # It *should* be handled with a fix to the OpenROAD Verilog parser.
+    # The following is a naive workaround to OpenROAD not accepting defparams.
+    # It *should* be handled with a fix to the OpenROAD Verilog parser.
     if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
         puts_info "This is a Synthesis Exploration and so no need to remove the defparam lines."
     } else {
@@ -122,7 +122,12 @@ proc run_synthesis {args} {
     TIMER::timer_stop
     exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "synthesis - yosys"
 
-    run_sta -pre_cts -log $::env(synthesis_logs)/sta.log -save_to $::env(synthesis_results)
+    run_sta\
+        -log $::env(synthesis_logs)/sta.log \
+        -netlist_in \
+        -pre_cts \
+        -save_to $::env(synthesis_results)
+
     set ::env(LAST_TIMING_REPORT_TAG) [index_file $::env(synthesis_reports)/syn_sta]
 
     if { $::env(CHECK_ASSIGN_STATEMENTS) == 1 } {