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IP layout design of a 8-bit Wallace tree Multiplier

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Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
notes		notes
rtl		rtl
sim		sim
tb		tb
README.md		README.md

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dvsd_wt3206m

IP layout design of a 8-bit Wallace tree Multiplier

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IP layout design of a 8-bit Wallace tree Multiplier

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Verilog 97.5%
Makefile 2.5%