Popular repositories Loading
-
-
cruz2324
cruz2324 PublicForked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python
-
tt06-verilog-template
tt06-verilog-template Public templateForked from TinyTapeout/tt06-verilog-template
Submission template for Tiny Tapeout 06 - Verilog HDL Projects
Tcl
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.