Vhdl xilinx spartan adcdela

Potrebujem pomoč pri programiranju modula Z-turn Board (Xilinx Zynq-7010/20) s programskim orodjem VIVADO. Program bo vseboval nekaj IIR in FIR filtrov, preproste matematične funkcije, sinusni generator, sinhroni demodulator ter vmesnike SPI za en A/D konverter in pet D/A konverterjev. Nastavljanje parametrov (konstant) ter zajem podatkov bo z ARM SoC na istem modulu z Linuxom.

I'm seeking an experienced developer to create a Microcontroller based main board & write the software for me. Key Project Specifications: - The board should feature a 2 channel ADC for precision temperature measurement from Type K, R and S type thermocouples. - I prefer the use of the STM32 microcontroller family for this main board. - Communication interfaces supported by the main board should include I2C, SPI, UART, ADC, RS485, and RTC. Deliverables Expected: 1. Three fully assembled and programmed PCBs ready for testing. 2. Complete source code for the project. 3. Schematic and Gerber files, including a pick and place file for PCB assembly. 4. Bill of Materials (B.O.M.) with vendor information. Ideal Skills and Experience: - Proficient in STM32 microcontrolle...

We are seeking assistance from an experienced freelancer who has worked on executing AI models on Xilinx-based FPGAs through TVM. The goal is to execute AI models trained with TensorFlow on a Xilinx FPGA, specifically the Ultra96v2 board. We are following the guidelines to execute a TVM-compiled AI model using the Vitis AI DPU. We are looking for validated tips to solve each issue and require remote support or virtual meetings. The available platforms for remote assistance include Skype, Zoom, Webex, and Microsoft Teams. Currently, we are using TensorFlow version 2.18, PYNQ version 3.0.1, Vitis AI version 2.5, and TVM version 0.19. 1. TensorFlow Model Conversion Error While following the example (), to convert a TensorFlow

I'm looking for a skilled engineer with experience in Altera FPGA and electronics to develop a smart automatic door lock system. The system should use an electronic strike solenoid lock and operate based on a 4x3 keypad input. Key project requirements: - The lock should open when a correct passcode is entered. There will be three different passcodes programmed into the system. - If the u...provide feedback when the correct passcode is entered. You will also need to provide guidance on how to connect the GPIO pins of the Altera DE0 Nanobot to a servo motor to simulate the door opening. The ideal candidate for this project should have a strong background in FPGA programming, electronics, and working with solenoid locks. Experience with Altera DE0 Nanobot is a plus. The code should be ...

Hi! I'm seeking a developer to create custom firmware for the nRF52840 and nRF52832, leveraging the nRF Connect SDK. The firmware should include the following features: ADC Measurement: Capture ADC data via the TWI interface using the AD5593 IC. LoRa Communication: Integrate and enable the RFM95 module to send data via LoRa. Bluetooth Advertising: Enable BLE advertising to broadcast the collected data. I currently have a working solution built with the nRF52 SDK (version 17.1.0), but I need the firmware to be migrated and fully implemented in the newer nRF Connect SDK. Thank you for your time and consideration! Please let me know if you're interested or have any questions. Best regards,

Hi, I need an APP optimized for Markov Chain Monte Carlo (MCMC) computations written in hardware description languages VHDL or Verilog for the AMD Alveo™ U50 Data Center Accelerator Card. The app should be as basic as possible, but it needs to outperform the top-performance CPUs such as Ryzen 9 7950x or IntelCore i9 14900K. AMD Alveo™ U50 Data Center Accelerator Card The app will be used for mining (PoW) activities for the Matrix AI Network project: From the MATRIX 1.0 White Paper, the recommended hardware for mining activities should focus on devices optimized for Markov Chain Monte Carlo (MCMC) computations. These computations are integral to the

I'm working on a digital circuit design project focused on a finite state machine (FSM) for a lock system. I need assistance with the design and implementation using VHDL on a Basys3 FPGA board. Ideal Skills: - Proficiency in VHDL - Experience with digital circuit design - Familiarity with FSMs Key Tasks: - Design a FSM for a lock system - Implement the design using VHDL - Test the design on a Basys3 FPGA board Please provide examples of similar projects you've completed in your proposal.

...advanced ESP32 developer to help me connect a 3.5mm headphone with mic to an ESP32 and turn it into a hands-free device for calls. I have a full working example at the provided Github link. However, this example expects an external DAC or codec. I want to use the internal DAC and ADC and connect to a TRRS adapter. Your guidance and code will be crucial for this project. Working code But this assumes an external dac and adc according to my knowledge I want to use internal one and connect it to the 3.5mm adapter. I need a circuit diagram and code. Key Requirements: - The device must support answering and ending calls. - Expertise in ESP32 development is a must. - Previous experience with Bluetooth

I require assistance with a project involving Xilinx ISE Design software version 14.7. The project encompasses a sign calculator and the implementation of LED patterns & seven segment display on the FPGA. Here's a more detailed breakdown of the tasks: - **Sign Calculator Implementation**: - The calculator should support basic arithmetic operations such as addition, subtraction, multiplication, and division. - It should be designed using a combination of combinational and sequential logic using Verilog. - **LED Patterns on FPGA**: - The LED patterns should be generated randomly. - You should have experience in creating dynamic and visually appealing patterns. - **Seven Segment Display on FPGA**: - The project involves configuring a seven segment display on the F...

I'm seeking an FPGA expert proficient in VHDL for a multi-part project. The centerpiece is a digital alarm clock displayed on an LCD, with the following tasks to be completed: 1) A counter that counts from 0000-9999. It should be able to reset and be controlled using a pushbutton, displaying in decimal on 7-segment displays. 2) A digital alarm clock. The clock should display on an LCD and turn on an LED when the current time matches the alarm time. 3) Generation of a waveform. 4) Configuration of pins. 5) A demo video of the completed project. The digital alarm clock is the highest priority, so experience with time-based VHDL projects will be advantageous. Please note, the digital alarm clock does not need to include additional features such as a snooze function or mul...

Project Requirement: Line Recorder with Bluetooth Objective: Develop a compact Line Recorder device with Bluetooth connectivity that connects to a mobile app for controlling and managing call recordings. Key Features 1. 3.5mm Audio Connectivity: * Input Port (IN): C... * Start/Stop Recording: Signal the device to begin or stop recording. * Download Recordings: Retrieve the recorded audio file via Bluetooth. * Clear Storage: Automatically delete the recording after download. 3. Recording Capabilities: * Record audio passing through the 3.5mm * Use the ESP32’s internal ADC for recording,We just require normal speech quality data. If this does not work at all then consider using an external i2c or some adc that is cheap We will develop the ...

I'm seeking an expert FPGA designer with Verilog proficiency to develop a custom hardware accelerator. Key Responsibilities: - Design an FPGA-based hardware accelerator specifically for managing sequential DMA reads and writes for memory access (TRBs). - Implement this using Verilog. Requirements: - Extensive experience with Xilinx FPGA family. - Proficiency in Verilog. - Prior work in designing custom hardware accelerators. - Knowledge in handling DMA operations. - Ability to translate complex hardware functions into Verilog code. The goal of this project is to create an efficient, reliable hardware solution that can handle specific memory access tasks with optimal performance.

I'm in need of a professional who can assist me with simulating sequential logic circuits, specifically flip-flops and latches, using VHDL. Key Responsibilities: - Simulate sequential logic circuits using VHDL - Focus on flip-flops and latches Ideal Skills: - Proficiency in VHDL - Experience with simulating sequential logic circuits - Understanding of flip-flops and latches Your expertise will be pivotal in ensuring the successful simulation of these circuits. Looking forward to your proposals.

Request for Assistance from an Experienced Freelancer with Running AI Models on Xilinx FPGA Using TVM We are looking for an expert with experience in running AI models on Xilinx-based FPGAs using TVM. We need someone who can provide tips for resolving issues through video tutorials or documentation. If necessary, we are open to remote support or virtual meetings to address the problems. Our goal is to run AI models trained in TensorFlow on a Xilinx Ultra96v2 FPGA board. Following the instructions provided in the linked guide, we are executing AI models compiled with TVM using the Vitis AI DPU. The tools and versions currently being used are as follows: • PYNQ: Version 3.0.1 • Vitis AI: Version 2.5 • TVM: Version 0.19 Below are the issues we need help res...

I am looking for a professional with extensive knowledge in computer architecture to assist with an upcoming project. The ideal candidate should have a strong background in processor design, memory hierarchy, and I/O systems. Experience with performance optimi...with performance optimization, power efficiency, and scalability is a plus. Key Skills & Experience: - Extensive knowledge in computer architecture - Strong background in processor design, memory hierarchy, and I/O systems - Experience with performance optimization, power efficiency, and scalability - Proficiency in simulation or modeling tools related to computer architecture. - Proficiency in VHDL/Verilog for hardware design. Deliverable is a comprehensive technical report. The main objective is to create a video fo...

I need a professional to design and develop a low-noise PCB based on the ESP32-S3. The board must include an External Flash/PSRAM, ADS1256 ADC, USB-C, and a battery management system. - Primary Application: This PCB is meant for an IoT device, so the design should reflect the needs of this specific application. - Key Feature: The most critical aspect of this IoT device is its wireless connectivity. Therefore, the design and components must facilitate robust, efficient, and reliable wireless performance. - Connectivity Requirements: The device will primarily use Wi-Fi, so the PCB and its components must support and optimize for this type of wireless connectivity. - Integrate EMI shielding techniques to minimize electromagnetic interference with the IoT device's components. - I...

I need an expert to create a single lane bidirectional differential sender/receiver that connects two Xilinx FPGAs. Key Requirements: - The main purpose of this connection is data transfer between the two FPGAs. - The target data transfer rate is up to 1 Gbps (typ. 500 MBaud in DDR fashion) Ideal Skills: - Proficiency in FPGA programming, particularly with Xilinx FPGAs. - Familiarity with the SerDes, IO-Delay, clocking archtecture of Spartan-6 - Language: VHDL Please do not post any suggestions unless you have experience in VHDL coding.

I am searching for someone to help me with the following project. I hope you can help me. I need an APP optimized for Markov Chain Monte Carlo (MCMC) computations written in hardware description languages VHDL or Verilog for the AMD Alveo™ U50 Data Center Accelerator Card or similar other FDPA. The app should be as basic as possible, but it needs to outperform the top-performance CPUs such as Ryzen 9 7950x or IntelCore i9 14900K. AMD Alveo™ U50 Data Center Accelerator Card The app will be used for mining (PoW) activities for the Matrix AI Network project: From the MATRIX 1.0 White Paper, the recommended hardware for mining activities should focus on devices

I'm in need of a professional logo that integrates a spartan-style helmet with an airplane (not a jet), for my aviation business "Spartan Aero". Key Requirements: - Incorporate specific color palette: Blues and Grays. No bright or neon colors. - Create a clean, sleek, and versatile design. - The logo must function well in both print and digital media. Please note that I have a sample of a similar design which I can share. This design is just for inspiration and should not be copied. Ideal skills for this project: - Extensive experience in logo design. - Ability to understand and translate ideas into a visual design. - Strong communication skills for understanding project requirements and providing updates. No additional elements or symbols are required be...

Spyglas,VCS,DC,DFT,Verdi,Catapult,Synplify,VerilogXL,Virtuoso,Xcelium,Spectre,Allegro,Vivado,Quartus,ModleSim, Matlab,Octave,Signal Generator,Logic Analyzer,Anaconda,Tensorflow,Keras,Darknet ,notepad++. Language mastery: Verilog,SystemVerilog,UVM,C,C++,VHDL,Python,Firmware etc. Familiar with using: Linux, Windows,Unix,MS-DOS,FreeRTOS. PreviousFields: AISC/IP/IC design,SOC design/verification,FPGA Design/Verification and debugging,AI (especially deep learning),complex digital systems,complex communication systems,mixed digital and analog systems. Work experience focused in Beijing China 5+ years of ASIC experience and 10+ years of FPGA experience, experienced Senior Technical Lead with a demonstrated history of working in the semiconductors industry. Part of 5+ tape outs....

I'm looking for an expert who can implement a 1D deep learning inference accelerator on an FPGA. The primary objective is to optimize resource usage, with a specific focus on balancing power and resource efficiency. Work on vitis hls xilinx Key Requirements: - Experience with FPGA programming and optimization - Familiarity with Fully Connected Networks - Ability to balance power consumption and resource efficiency I want this project to be able to support fully connected networks primarily, so deep learning experience with these types of models is crucial. The ideal freelancer for this job will not only have technical expertise, but also a strong understanding of how to maximize efficiency in both power usage and resource allocation.

The company is seeking FPGA Designers proficient in VHDL to outsource specific tasks. Some tasks will require a remote server connection for accessing resources and collaborative development. Skills Required: Proficiency in VHDL for FPGA design and development. Experience with simulators such as ModelSim or Active-HDL/Riviera. Additional Skills (Considered a Plus): Expertise in synthesis and implementation processes. Proficiency in Tcl scripting for automation and tool customization. Experience with debugging and testing using tools like ILA (Integrated Logic Analyzer), SignalTap, or similar. Familiarity with embedded software development, including: Writing bare-metal C/C++ for testing Zynq firmware. Developing or customizing a complete PetaLinux OS. Soft Skills: Stro...

We are seeking a skilled Embedded Software Engineer with expertise in developing and integrating software for embedded systems. This role involves working closely with FPGA designs and ensuring seamless software functionality for various applications. If you have experience in C/C++, Linux for embedded systems, and custom driver development, we’d love to hear from you. Prior experience with Xilinx Zynq devices is a significant advantage. Key Responsibilities: Develop and maintain embedded software for systems interfacing with FPGA designs. Implement software solutions in C/C++ for embedded applications. Design and integrate custom drivers in both kernel and user space. Work with Linux-based embedded systems, including Petalinux and Yocto Project. Collaborate with hardware e...

I am working on a tensile testing device project as a university student. For this project, an embedded software needs to be developed to coordinate various hardware components connected to a Raspberry Pi. The hardware components to be used are: Loadcell: Measures force and sends data to the Raspberry Pi through an ADC (e.g., HX711). Strain Gauge: Used to measure deformation in the material and also connected via an ADC. Servo Motor: Controls the loading process; position and speed will be adjusted using PWM signals. Camera (Raspberry Pi V2): Used for image processing (this part will be handled by a separate software). Software Responsibilities: Read and process data from the loadcell and strain gauge. Control the servo motor for loading and stopping actions. Calculate para...

I'm looking for an experienced professional to help debug my Verilog code, Xilinx Vivado, FPGA; specifically focusing on UART communication related to data transmission. I'm currently at the final testing stage and encountering issues with incorrect data output. Key Requirements: - Expertise in UART communication, particularly in data transmission - Proficiency in Verilog coding - Experience in debugging and troubleshooting Verilog code - Ability to identify and resolve issues causing incorrect data output - Familiarity with simulation software such as ModelSim or Vivado

I'm seeking a skilled technical writer with a strong background in VLSI digital design to create an educational document aimed at intermediate learners. The document should focus on HDL (Verilog/VHDL) and provide clear, comprehensive explanations of the concepts, techniques, and applications pertinent to this area of digital design. Key Requirements: - In-depth knowledge and experience in VLSI digital design and HDL (Verilog/VHDL). - Proven technical writing skills, particularly in creating educational materials. - Ability to explain complex concepts in an accessible way for intermediate learners. The final document should be well-structured, engaging, and suitable for use as a teaching resource. The document should be between 25-50 pages.

I am searching for someone to help me with the following project. I hope you can help me. I need an APP optimized for Markov Chain Monte Carlo (MCMC) computations written in hardware description languages VHDL or Verilog for the AMD Alveo™ U50 Data Center Accelerator Card or similar other FDPA. The app should be as basic as possible, but it needs to outperform the top-performance CPUs such as Ryzen 9 7950x or IntelCore i9 14900K. AMD Alveo™ U50 Data Center Accelerator Card The app will be used for mining (PoW) activities for the Matrix AI Network project: From the MATRIX 1.0 White Paper, the recommended hardware for mining activities should focus on devices

I am searching for someone to help me with the following project. I hope you can help me. I need an APP optimized for Markov Chain Monte Carlo (MCMC) computations written in hardware description languages VHDL or Verilog for the AMD Alveo™ U50 Data Center Accelerator Card or similar other FDPA. The app should be as basic as possible, but it needs to outperform the top-performance CPUs such as Ryzen 9 7950x or IntelCore i9 14900K. AMD Alveo™ U50 Data Center Accelerator Card The app will be used for mining (PoW) activities for the Matrix AI Network project: From the MATRIX 1.0 White Paper, the recommended hardware for mining activities should focus on devices

I am searching for someone to help me with the following project. I hope you can help me. I need an APP optimized for Markov Chain Monte Carlo (MCMC) computations written in hardware description languages VHDL or Verilog for the AMD Alveo™ U50 Data Center Accelerator Card or similar other FDPA. The app should be as basic as possible, but it needs to outperform the top-performance CPUs such as Ryzen 9 7950x or IntelCore i9 14900K. AMD Alveo™ U50 Data Center Accelerator Card The app will be used for mining (PoW) activities for the Matrix AI Network project: From the MATRIX 1.0 White Paper, the recommended hardware for mining activities should focus on devices

Development of a multichannel sensor array with TCP/IP data transport. Familiarity with implementation of a full network stack and bridging to sensor subsystems. The system should handle moderate data rates. Sensor linearization and PID control will be performed on ...transport. Familiarity with implementation of a full network stack and bridging to sensor subsystems. The system should handle moderate data rates. Sensor linearization and PID control will be performed on future versions of the system. DSP layers for basic spectral filtering as well as array sensitivity optimization algorithms to be developed The development platform for the FPGA will be Xilinx and the first phase of the project will utilize an existing code base that has undergone significant testing on prior...

I need help in a project. All what I have to do is already given (manual). I need help to do the exercises given

...firmware for my production hardware. The hardware is currently in the testing phase. Key Requirements: - The firmware must support various STM32 peripheral functions, including ADC with DMA, Timers for PWM/SPWM, and UART communication. - Expertise in STM32 programming with HAL and STM32CubeMX is crucial. - Experience with FreeRTOS integration and task management is necessary. - The firmware must include support for I2C and SPI peripheral functions for sensor and peripheral communication. - The firmware must have robust error handling and diagnostics to ensure reliable operation. Ideal Skills: - Proficient in using ADC with DMA for data acquisition - Skilled in configuring Timers for PWM/SPWM for motor control - Adept at establishing UART communication for the communic...

I need an expert with experience on methods for amplifying a photodiode signal, and designing a schematic for this circuit. I do not need a PCB yet. I already have a high-bandwidth transimpedance amplifier circuit with a reverse-biased photodiode, connected to an ADC input as well as a comparator. I need to detect light flashes in a variety of ambient light conditions (from darkness to direct sunlight), and my current circuit saturates the output in bright light. If I change the feedback resistor to avoid this, then it is not sensitive enough in low light. I am looking for advice on how best to deal with this and implement automatic gain control. Ideas include: - using multiple stages of amplification - using a PGA or VGA op-amp - using analog switches to select different value fe...

UPDATE: ATTENTION So I’m just now getting back to your messages and I’ve chosen a...including online, print, and on merchandise. The final designs must be adaptable to these formats. - Design: I'm open to a variety of styles, but I'm particularly interested in logos that are both bold and vibrant, as well as classic and elegant. A designer who can balance these qualities effectively would be ideal. Design requirements: • The first design I'm looking for needs to resemble a spartan helmet with a wreath around it or banner like below but I’m also open to designs see the photo below for example. Separate logo • Arrow head. I am open to suggestions and ideas. I've included two examples below. Please contact me if you need more inf...

• Description We are exploring FPGA programming to mine crypto. You are responsible for programming to set up a pilot study remotely. We are likely to go for Xilinx, but you can suggest otherwise. The end product/code will run on our FPGA device. You will be paid on the base rate for the project, plus a bonus of a % of the revenue generated. • Bidding Your bid is my budget. If you deliberately put in a low bid to attract me to speak to you, you either revise your bid, or I will ignore you. • Delivery We need the source code and will integrate your program into a much larger one. You will be paid once you finish all the work and it works on my machine. We will also attack your program, as it has to be secure and reliable without loopholes. It has to be bug-free. &b...

I'm seeking an ...FPGA software. Key Requirements: - PCB Design: As there are no pre-existing specifications, you will need to create detailed designs for the printed circuit board. - FPGA Software Development: The FPGA software will need to handle both protocol conversion and signal enhancement. Experience with Xilinx FPGA platforms is crucial. Ideal Skills: - PCB Design: Proficiency in designing PCBs with the ability to create detailed specifications. - FPGA Software Development: Extensive experience with Xilinx platforms and designing software for FPGA processors. - Signal Processing: Skill in enhancing signals during protocol conversion. - Communication: Ability to clearly articulate project progress and challenges. The expected timeline for project completion is ...

I need a freelancer who can design an 8-bit up/down counter on an FPGA for me. This counter should be binary based and capable of interfacing wit...binary based and capable of interfacing with a 10MHz clock. Key Requirements: - Design an 8-bit binary up/down counter - Implement 'clear' and 'load' features - Synchronize with a 10MHz clock Ideal Skills: - Proficiency in FPGA development - Experience with digital circuit design - Familiarity with binary counter design The counter should interface with an LED display for output. Please use a Xilinx FPGA platform for this project. The counter should reset to zero. Please ensure the counter can load a value from an input signal. The counter should be controlled using button input for up/down counting. Please use Ver...

I am seeking an experienced VHDL programmer to assist in the development of a digital circuit design for FPGA implementation. The project involves creating VHDL modules for a state machine-based system designed to generate and store Fibonacci numbers in RAM. The key components of this project include: Main FSM Controller: Develop a Finite State Machine (FSM) to manage the generation and storage of Fibonacci numbers, handling state transitions based on external inputs. Debouncer: Implement a debouncer module to stabilize the input signals from physical buttons, ensuring clean transitions and preventing bounce-related issues. Counter: Create a counter module that will provide address generation for the RAM, managing the read/write operations based on the FSM's state. R...

I'm looking for an experienced FPGA engineer, proficient with HLS, to implement the Viterbi (VIT) model on a Xilinx FPGA. The primary goal of this project is to significantly reduce the processing time for image data. Key requirements: - Extensive experience in FPGA programming, particularly with Xilinx platforms. - Proficient in High-Level Synthesis (HLS). - Prior experience with implementing the Viterbi model. - Strong understanding of image data processing. The ideal candidate will have a proven track record of successful FPGA projects, with the ability to deliver high-quality work under tight deadlines. Your expertise will help streamline our image data processing, making it faster and more efficient.

I'm seeking an expert in neuromorphic computing and coprocessor design for a university project. The primary deliverable is simulating the designed coprocessor using Verilog. Key project components include: - Designing a custom neuromorphic cop...neuromorphic computing and coprocessor design for a university project. The primary deliverable is simulating the designed coprocessor using Verilog. Key project components include: - Designing a custom neuromorphic coprocessor tailored for the project. - Producing simulation results using Verilog. Ideal skills and experience for the job: - Extensive experience with Verilog and other simulation tools. (Xilinx vivado) - Proven track record of designing and simulating custom hardware. - Ability to deliver high-quality, detailed simu...

...RISK-V CH32V003F4U (16K Flash) micro, leverage existing libraries for GPIO, ADC & I2C to create a LM81 like device. Work is simply to create a front-end I2C 7-bit slaver, add register access CMD/DATA like the LM81 to configure each pin as a ADC or GPIO, so a HOST I2C device can read the GPIO pins or set them. Key Responsibilities: - Utilize existing libraries for GPIO, ADC, and I2C - Implement a system for configuring each pin as either an ADC or a GPIO - Enable a HOST I2C device to read GPIO pins or set them - Provide I2C 7-bit Slave access - Allow for ADC readings and GPIO state reading and setting Essential Skills: - Proficient in C programming - Familiar with WCH RISK-V micro - Experience with I2C, GPIO, and ADC - Knowledge of LM81 de...

I'm looking for an experienced FPGA Verification engineer to help with unit testing my existing Verilog code. The primary focus will be on conducting functional tests to ensure the integrity and performance of the code. Ideal Skills: - Proficient in Verilog with significant experience in FPGA software engineering. - Stro...and implementing unit tests, specifically functional tests. - Familiarity with FPGA design and optimization. - Excellent problem-solving skills and attention to detail. Experience: - Proven track record of successful FPGA code testing. - Experience with Class C Software - Experience with writing code and unit test for medical devices - Experience with Verilog is essential, prior experience with VHDL or SystemVerilog is a plus. - Familiarity with Quartus ...

I am looking for a skilled professional with expertise in digital VLSI design and simulation-based verification. The primary focus of this project is on the design and verification of a digital VLSI ...the design and verification of a digital VLSI circuit. Ideal Skills and Experience: - Extensive experience in digital VLSI design. - Proficient in simulation-based verification methods. - Familiarity with various simulation tools and software. - Strong problem-solving skills and attention to detail. - Good communication skills to relay progress and challenges. - Proficiency in HDL languages like VHDL and Verilog. Key Responsibilities: - Designing a digital VLSI circuit. - Conducting thorough simulation-based verification. - Providing regular updates on progress and any challenges en...

Looking for someone with NTSC/PAL video encoding/decoding to help us with selecting the components for our projects. We are planning to use an FPGA for encoding/decoding, but would need help selecting appropriate ADC/DAC and possibly Video Filters or other things we may be forgetting. This should be a very simple job for somebody with the proper knowledge and experience. You would act as consultant and answer a few questions we may have. This will lead to a much bigger job for the full conception and development of the final product, but for now we would like to scope the project and make sure it's doable. Please provide details about your previous experiences with NTSC/PAL video format.

As discussed we need FPGA VHDL design for our ongoing projects

Create profesional c microcontroller code for : 1. input capture function as input signal hall sensor through pin CCP1 2. input capture for function speedometer in km/h with a circumference of wheel 700mm 3. microcontroller PIC8LF45K22 4. voltage battery monitoring 2.5V-3.3V through ADC 5. send raw value ADC and frequency to UART 6. send current result speed, odometer, and voltage to UART 7. if input captures signal inactive microcontroller in sleep mode 8. unused pin microcontroller status must be inactive (to reduce power consumption) 9. Clock microcontroller 16Mhz 10. interface microcontroller with GSM module 11. Send accumulation odometer every 100Km and battery monitoring to SMS 12. support request SMS from mobile phone to GSM module about current odometer and battery...

• Description We are exploring FPGA programming to mine crypto. You are responsible for programming to set up a pilot study remotely. We are likely to go for Xilinx, but you can suggest otherwise. The end product/code will run on our FPGA device. You will be paid on the base rate for the project, plus a bonus of a % of the revenue generated. • Bidding Your bid is my budget. If you deliberately put in a low bid to attract me to speak to you, you either revise your bid, or I will ignore you. • Delivery We need the source code and will integrate your program into a much larger one. You will be paid once you finish all the work and it works on my machine. We will also attack your program, as it has to be secure and reliable without loopholes. It has to be bug-free....

I'm looking for a Python expert to develop a package that automates the process of pulling VHDL code from a git repository, compiling it, running lint checks, simulating it, and generating documentation using custom scripts I've developed. Key features of the package should include: - Interfacing with a git repo to pull code - Using custom scripts for compilation, linting, simulation, and documentation - Outputting the results of simulations as log files Ideal candidate: - Extensive experience with Python - Familiarity with VHDL and git - Able to understand and work with custom scripts - Good understanding of software package development

...automation and managing virtual machines (VMs). Key Responsibilities: - Oversee our Citrix infrastructure, particularly Citrix Virtual Apps and Desktops and Citrix ADC (Netscaler). - Configure and maintain VMs using VMware, Hyper-V, and other similar platforms. - Implement and enhance UiPath automation processes primarily supporting our Finance, Accounting, and Customer Service functions. - Troubleshoot and resolve issues related to Citrix and VMs promptly. - Ensure secure access and optimal performance for our virtual environments. Ideal Skills and Experience: - Extensive experience with Citrix Virtual Apps and Desktops, Citrix ADC (Netscaler) and Citrix Cloud. - Proficiency in configuring and maintaining virtual machines on VMware and Hyper-V. - Proven track record in ...

I am looking for an expert in Verilog and Xilinx FPGA boards to help me with a project. The task involves controlling a servomotor based on the distance detected by an ultrasonic sensor. Essential Project Details: - The distance to be detected by the ultrasonic sensor falls within the medium range of 2 to 5 meters. - The control logic for the servomotor needs to be implemented in Verilog. Ideal Skills and Experience: - Proficiency in Verilog is mandatory. - Extensive experience with Xilinx FPGA boards is highly desirable. - Prior work with servomotor and ultrasonic sensor control is an advantage. - Ability to deliver a precise, reliable and efficient control system.