Verilog Design for 10GbE on Artix Ultrascale+
₹400-750 INR / godzinę
I'm seeking a skilled FPGA developer with comprehensive knowledge in Verilog and Ethernet standards. The project involves implementing a 10 Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) and Media Access Control (MAC) in an Artix Ultrascale+ FPGA, utilizing SFP+ ports.
Key Responsibilities:
- Design and implement a Verilog module for basic data transmission via 10GbE.
- Ensure compatibility with Artix Ultrascale+ FPGA.
- Utilize Vivado for all simulations, testing and final implementation.
Ideal Candidates:
- Proficient in Verilog and FPGA design, particularly with Artix Ultrascale+ series.
- Extensive experience with designing Ethernet PCS/PMA and MAC layers.
- Familiar with Vivado and its simulation capabilities.
- Able to deliver efficient, reliable and well-documented code.
Numer ID Projektu: #39003387
O projekcie
7 freelancerów złożyło ofertę na średnią kwotę ₹724/godzinę w tym projekcie
I have 18 years of experience in the field of electronics and have worked with various fpga architectures and projects
While I cannot directly implement the FPGA design myself, I can serve as an invaluable asset to your development team. I can significantly enhance your productivity, improve the quality of your code, and accelerate you Więcej
I have hands-on experience on Artix-7 FPGA and verliog coding over 2 years and professional experience of 1 year. Working on the Vivado platform for over 3 years and indulged with more than 2 FPGA.
I possess extensive expertise in Verilog HDL and FPGA-based design, with a proven track record in high-speed data transmission projects, including 10GbE. My experience includes implementing serialization, framing, and Więcej
In my early career I have worked on 10g ethernet Physical Coding Subblock (PCS) SO I am the good fit to this project Please contact me for further discussion Haritha: 9989316646
