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ASIC
FPGA
FPGA Coding
Verilog / VHDL
Very-large-scale integration (VLSI)
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Mohamed M.

@Majiidd

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Verilog/SV/VHDL RTL coding | FPGA | ASIC | VLSI

$10 USD / time
・
s flagg
Egypt (5:17 a.m.)
・
Ble med desember 7, 2022
$10 USD / time
・
Digital IC Design RTL Modeling, FPGA & IP/SoC Embedded Development Engineer. Offering: - FPGA/ASIC RTL solutions in (System)Verilog, and VHDL. - Embedded C Coding. - Multilingual Tutoring. -------Your success is my priority------- Available Round-the-Clock | Flexible Pricing | Prioritizing Service Excellence My Experience: I've worked extensively with FPGAs, utilizing various FPGA boards from different vendors such as AMD(Xilinx)/Intel(Altera)/Efinix. Also experienced in ASIC designs, I've worked with Synopsys tools, with TCL scripts and GUI for DesignCompiler, Formality. Proficient in documentation using: - LaTeX: for professional documentation. - Markdown: for GitHub repos. - Microsoft Word. Let's collaborate and bring your project to life. Reach out to discuss the details, and I'll be here to assist you at any time. Additional Key Skills: - STA and CDC. - Communication protocols such as: UART - SPI - I2C - AXI. - Programming languages such as: Python - C/C++. - Knowledge in scripting Language : TCL. Tools: Vivado IDE • Quartus prime • Efinity IDE • VS Code • Xilinx ISE • ModelSim/QuestaSim • Synopsys DesignCompiler • MATLAB • Git/GitHub • Logisim.
Verifikasjoner
Akseptrate
100 %
Freelancer Verilog / VHDL Designers Egypt
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Portefølje

Portefølje

10713522
An RTL modeling for a wash machine controller, using Verilog HDL. -Designed a controller for a washing machine that has the following states: --IDLE --FILLING WATER --WASHING --RINSING --SPINNING -also supports the following: -A double wash option. -A timer pause during the spinning phase. -Multiple operating frequencies. -An asynchronous active low reset. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/Washing-Machine
Washing Machine Controller, using Verilog HDL.
An RTL modeling for a wash machine controller, using Verilog HDL. -Designed a controller for a washing machine that has the following states: --IDLE --FILLING WATER --WASHING --RINSING --SPINNING -also supports the following: -A double wash option. -A timer pause during the spinning phase. -Multiple operating frequencies. -An asynchronous active low reset. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/Washing-Machine
Washing Machine Controller, using Verilog HDL.
10713500
Summary UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART
Full UART implementation using Verilog HDL
Summary UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART
Full UART implementation using Verilog HDL
Summary UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART
Full UART implementation using Verilog HDL
10713442
Implementation of 32-bit Single-Cycle MIPS processor based on Harvard architecture, MIPS processor is from the RISC family, It supports 3 different types of instructions such as: R-Type, I-type, and J-type. It is supported with a CLA Adder -Carry Look Ahead Adder- for fast computations. The architecture relies on 3 main components: -Control Unit. -Data Path. -Data/Instruction Memory. For detailed information visit my GitHub: https://github.com/MuhammadMajiid/MIPS-Processor
Implementation of 32-bit MIPS-processor using SystemVerilog
10713425
Implementation of the 128-bit AES protocol is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001. AES is widely used today as it is a much stronger than DES and triple DES despite being harder to implement. -Points to remember: --AES is a block cipher. --The key size can be 128/192/256 bits. --Encrypts data in blocks of 128 bits each. That means it takes 128 bits as input and outputs 128 bits of encrypted cipher text as output. AES relies on substitution-permutation network principle, which means it is performed using a series of linked operations involving replacing and shuffling the input data. -Working of the cipher : AES performs operations on bytes of data rather than in bits. Since the block size is 128 bits, the cipher processes 128 bits (or 16 bytes) of the input data at a time. for more information visit my GitHub: https://github.com/MuhammadMajiid/AES
Advanced Encryption Standard (AES) modelling, using Verilog
10713522
An RTL modeling for a wash machine controller, using Verilog HDL. -Designed a controller for a washing machine that has the following states: --IDLE --FILLING WATER --WASHING --RINSING --SPINNING -also supports the following: -A double wash option. -A timer pause during the spinning phase. -Multiple operating frequencies. -An asynchronous active low reset. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/Washing-Machine
Washing Machine Controller, using Verilog HDL.
An RTL modeling for a wash machine controller, using Verilog HDL. -Designed a controller for a washing machine that has the following states: --IDLE --FILLING WATER --WASHING --RINSING --SPINNING -also supports the following: -A double wash option. -A timer pause during the spinning phase. -Multiple operating frequencies. -An asynchronous active low reset. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/Washing-Machine
Washing Machine Controller, using Verilog HDL.
10713500
Summary UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART
Full UART implementation using Verilog HDL
Summary UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART
Full UART implementation using Verilog HDL
Summary UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin. For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART
Full UART implementation using Verilog HDL
10713442
Implementation of 32-bit Single-Cycle MIPS processor based on Harvard architecture, MIPS processor is from the RISC family, It supports 3 different types of instructions such as: R-Type, I-type, and J-type. It is supported with a CLA Adder -Carry Look Ahead Adder- for fast computations. The architecture relies on 3 main components: -Control Unit. -Data Path. -Data/Instruction Memory. For detailed information visit my GitHub: https://github.com/MuhammadMajiid/MIPS-Processor
Implementation of 32-bit MIPS-processor using SystemVerilog
10713425
Implementation of the 128-bit AES protocol is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001. AES is widely used today as it is a much stronger than DES and triple DES despite being harder to implement. -Points to remember: --AES is a block cipher. --The key size can be 128/192/256 bits. --Encrypts data in blocks of 128 bits each. That means it takes 128 bits as input and outputs 128 bits of encrypted cipher text as output. AES relies on substitution-permutation network principle, which means it is performed using a series of linked operations involving replacing and shuffling the input data. -Working of the cipher : AES performs operations on bytes of data rather than in bits. Since the block size is 128 bits, the cipher processes 128 bits (or 16 bytes) of the input data at a time. for more information visit my GitHub: https://github.com/MuhammadMajiid/AES
Advanced Encryption Standard (AES) modelling, using Verilog
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Utdanning
Alexandria University
2019 - 2024
•
5 år
Bachelor degree of Electronics and Electrical Communication Engineering
s flagg
Egypt
2019 - 2024
•
5 år
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