Urgent Verilog Code Logic Design - Urgent

At the start of each round the Game Counter is displayed on the rightmost two digits of the BASYS3 7-segment display. The left two digits are off. A go_i signal is given (pushbutton btnC is pressed) to start the next round. In each round, a random 5-bit binary value, the target number, is selected and displayed on the two leftmost digits and the 5-bit Game Counter (still displayed on the rightmost digits) is set to 1f. After 2 seconds the Game Counter begins to decrement every quarter second. The Game Counter will keep decrementing, rolling under to 1f (31 decimal) after reaching 0. When the stop_i signal is given (pushbutton btnU) the Game Counter stops decrementing. At this point, if the value of the Game Counter matches the target number, then all 4 display digits flash for four seconds in unison. If the value of the Game Counter does not match the target number, then all 4 display digits flash for four seconds, with the target number and Game Counter digits alternating as they flash. The flashing continues for four seconds and then the leftmost digits are again blank and a new round can begin with a go_i signal. Each time the player succeeds in matching the target, one more LED lights up beginning with the rightmost. If all 16 LEDs are lit, and the target number was matched, then the game has been won. After the digits flashes for 4 seconds, all 16 LEDs flash, and no button, except btnR will have an effect. To make the game easier to win (without 17 matches), pressing btnL will be a cheat switch that will load the switches into the LEDs (or actually the shift register holding the values of the LEDs). On the BASYS3 board, PushButton btnC drives the go_i signal. PushButton btnU drives the stop_i signal. PushButton btnL will load the switches into the LEDs. PushButton btnR drives the synchronous active-low global reset rst_ni. The BASYS3 clock clk_100 is an input of your top level, but will not be part of your logic. It is connected only to the clk_100M_to_clk_1k and clk_100M_to_clk_4 clock divider modules, which divides the 100 MHz clock into 1 kHz and 4 Hz respectively. I have most of code done You will need to run make lint, make sim and make gls to ensure the codes work.