Shai K.

A highly motivated FPGA Design Engineer and Project Manager with +10 years of experience. I'm always looking for new challenges and have a great thirst for knowledge. I worked for large companies as well as emerging Start-Ups developing new game-changing technologies in the fields of Medical, Defense, Automotive and Communications. My experience involves designing solutions from the ground up from Specifications Characterization to High Level Design, Writing Code, Code Review , Simulation, Integration and Debugging. I'm experienced with the following FPGA families: Xilinx on Vivado: Kintex 7, Virtex 7, Kintex Ultrascale, Zynq 7000 and Zynq MPSOC (as well as older families). Altera (Intel) on Quartus: Cyclone V SOC, Arria V SOC, Stratix V and Arria 10. I've implemented the following algorithms in pure HDL (VHDL as well as Verilog): Image Enhancement, Image Rotation, Temporal 2D IIR and 2D FIR filters for noise reduction. Edge Detection, 2D Box Filter Convolutions, Sensor Dark Correction, Histogram Calculation and Equalization, Alpha Blending on Screen Overlay and Video Frame Buffering.