I am a researcher in hardware security and a circuit designer for floating-point arithmetic cores, DSP cores in HDL/schematic. I have the scientific journal published in these areas with patent. I assure you that your needs will be fulfilled in an HDL/circuit schematic with optimized for area, delay, and speed point of views. Additionally, pipeline, datapath subsystem, and static timing analysis in digital circuit implementation are performed. Specialist in hardware architectures for arithmetic blocks, signal processing, cryptography, machine learning architectures and computer architecture Having 10 years experience in hardware design, verilog/VHDL and circuit simulation at Intel Quartus II, Cadence SoC encounter/RTL compiler, LTspice, Logisim and Microwind DSCH DOMAINS VLSI- ASIC/FPGA CMOS layout CMOS stick diagrams Physical design Digital hardware implementation AI hardware in VLSI Microprocessors and Micro controller implementations in FPGA DSP/Embedded Hardware High-level algorithms into hardware Computer Architecture Network on chip Memory circuit design Finite state machine design SKILLS Verilog/VHDL TCL script A circuit schematic, state machine/table, RTL coding Pipeline, retiming, Cross-domain clocking, High level synthesize Asynchronous timing, bus protocols (AMBA, PCIe, SPI, I2C) TOOL EXPERT Quartus II prime EDA Cadence NCSIM- verilog simulation Cadence RTL compiler Cadence SoC encounter/180 nm technology node Modelsim Microwind Logisim LTspice Ledit Xilinx VIvado HLS