@database "AGA.guide"

@width 80

##

## $VER: AGA.guide 1.0 (29.Aug.93)

## Done by T.F.A. 1993

##

## Pandore ChipSet AmigaGuide® documentation.

##

##

## Contents

##

@node main "Pandora Chipset Documentation"

(C) 1993 by TFA

-- - --+- -- - -+*>> ArTiSt'S WiTh An AtTiTuDe <<*+- - -- -+-- -

Specification for the

Advanced Amiga (AA) Chip Set

TYPED BY FIREFLASH/C18,SPONGE/C18

AMIGAGUIDE VERSION & PAGE 19 BY SCHWARZENEGGER/TFA

Please select any of the topics listed below and follow up on the links

as they appear.

@{"1. Summary of new features for AA" link summary }

@{"2. Explanation of new features" link explanation }

@{"3. List of Registers ordered by address" link registersindex }

@{"4. List of Registers ordered alphabetically" link moreregisters }

@{"5. New LISA Display & Sprite Modes" link LisaModes }

@endnode

@node summary

1. Summary of new features for AA

---------------------------------

32 bit wide data bus supports input of 32-bit wide bitplane data and allows

doubling of memory bandwidth. Additional doubling of bandwidth can be

achieved by using FAST page mode Ram. The same bandwidth enhancements are

available for sprites. Also the maximum number of bitplanes useable in all

modes was increased to eight (8).

The color Palette has been expanded to 256 colors deep and 25 bits wide (8

RED,8 GREEN,8 BLUE,1 GENLOCK). This permits display of 256

simultaneous colors in all resolutions. A palette of 16,777,216 colors are

available in all resolutions.

28Mhz clock input allows for cleaner definition of HIRES and SHRES pixels

ALICE`S clock genarator is synchronized by means of LISA`s 14MHz and SCLK

outputs, Genlock XCLK and XCLKEN pins have been eliminated (external MUX is

now required).

A new register bit allows sprites to appear in the screen border regions

(BRDRSPRT - See @{"BPLCON3" link BPLCON3}).

A bitplane mask field of 8 bits allows an address offset into the color

palette.

Two 4-bit mask fields do the same for odd and even sprites.

In Dual Playfield modes,2 4-bitplane playfields are now possible in all

resolutions.

Two Extra high-order playfield scrollbits allow seamless scrolling of up to

64 bit wide bitplanes in all resolutions. Resolution of bitplane scroll,

display window,and horizontal sprite position has been improved to 35ns in

all resolutions.

A new 8-bitplane HAM mode has been created, 6 for colors and 2 for control

bits. All HAM modes are available in all resolutions (not just LORES as

before).

A RST_input pin has been added, which resets all the bits contained in

registers that were new for ECS or LISA:

@{"BPLCON3" link BPLTCON3}, @{"BPLCON4" link BPLCON4}, @{"CLXCON2" link CLXCON2}, @{"DIWHIGH" link }, @{"FMODE" link FMODE}.

Sprite resolution can be set to LORES,HIRES,SHRES,independant of bitplane

resolution.

Attached Sprites are now available in all resolutions.

Hardware Scan Doubling support has been added for bitplanes and sprites.

This is intended to allow 15KHz screens to be intelligently displayed on a

31KHz monitor and share the display with 31KHz screens.

@endnode

@node explanation

2. Explanation of new features

------------------------------

Bitplanes

---------

There are now 8 bitplanes instead of 6. In single playfield modes they can

address 256 colors instead of 64. As long as the memory architecture can

support the bandwidth, all 8 bitplanes are available in all 3 resolutions

In the same vein, 4+4 bitplane dualplayfield is available in all 3

resolutions, unless bitplane scan-doubling is enabled, in which case

both playfields share the same bitplane modulus register. Bits 15 thru 8 of

@{"BPLCON4" link BPLCON4} comprise an 8 bit mask for the 8 bitplane address, XOR`ing the

individual bits. This allows the copper to exchange color maps with a

single instruction.

@{"BPLCON1" link BPLCON1} now contains an 8 bit scroll value for each of the playfields.

Granularity of scroll now extends down to 35nSec.(1 SHRES pixel), and

scroll can delay playfield thru 32 bus cycles. Bits BPAGEM and BPL32

in new register @{"FMODE" link FMODE} control size of bitplane data in @{"BPL1DAT" link BPLxDAT} thru @{"BPL8DAT" link BPLxDAT}.

The old 6 bitplane HAM mode, unlike before, works in HIRES and SHRES

resolutions.

As before bitplanes 5 and 6 control it`s function as follows:

+-----+-----+--------+--------+------------------+

| BP6 | BP5 | RED | GREEN | BLUE |

+-----+-----+--------+--------+------------------+

| 0 | 0 | select new base register (1 of 16) |

+-----+-----+--------+--------+------------------+

| 0 | 1 | hold | hold | modify |

+-----+-----+--------+--------+------------------+

| 1 | 0 | modify | hold | hold |

+-----+-----+--------+--------+------------------+

| 1 | 1 | hold | modify | hold |

+-----+-----+--------+--------+------------------+

There is a new 8 bitplane HAM (Hold and Modify) mode. This mode is invoked

when BPU field in @{"BPLCON0" link BPLCON0} is set to 8 , and HAMEN is set. Bitplanes 1 and 2

are used as control bits analagous to the function of bitplanes 5 and 6 in

6 bitplane HAM mode:

+-----+-----+--------+--------+------------------+

| BP2 | BP1 | RED | GREEN | BLUE |

+-----+-----+--------+--------+------------------+

| 0 | 1 | select new base register (1 of 64) |

+-----+-----+--------+--------+------------------+

| 0 | 1 | hold | hold | modify |

+-----+-----+--------+--------+------------------+

| 1 | 0 | modify | hold | hold |

+-----+-----+--------+--------+------------------+

| 1 | 1 | hold | modify | hold |

+-----+-----+--------+--------+------------------+

Since only 6 bitplanes are available for modify data, the data is placed in

6 MSB. The 2 LSB are left unmodified, which allows creation of all

16,777,216 colors simultaneously, assuming one had a large enough screen

and picked one`s base registers judiciously. This HAM mode also works in

HIRES and SHRES modes.

For compatibility reasons EHB mode remains intact. Its existence is rather

moot in that we have more than enough colors in the color table to replace

its functionality. As before, EHB is invoked whenever SHRES = HIRES =

HAMEN= DPF = 0 and BPU = 6. Please note that starting with ECS DENISE

there is a bit in @{"BPLCON2" link BPLCON2} which disables this mode (KILLEHB).

Bits PF2OF2,1,0 in @{"BPLCON3" link BPLCON3} determine second playfield`s offset into the

color table. This is now necessary since playfields in DPF mode can have up

to 4 bitplanes. Offset value are as defined in register map.

BSCAN2 bit in @{"FMODE" link FMODE} enables bitplane scan-doubling. When V0 bit of @{"DIWSTRT" link DIWSTRT}

matches V0 of vertical beam counter, @{"BPL1MOD" link BPL1MOD} contains the modulus for the

display line, else @{"BPL2MOD" link BPL2MOD} is used. When scan-doubled both odd and even

bitplanes use the same modulus on a given line, whereas in normal mode odd

bitplanes used BPL1MOD and even bitplanes used BPL2MOD. As a result Dual

Playfields screens will probably not display correctly when scan-doubled.

Sprites

-------

Bits SPAGEM and SPR32 in @{"FMODE" link FMODE} whether size of sprite load datain

@{"SPR0DATA(B)" link SPRxDAT} thru @{"SPR7DATA(B)" link SPRxDAT} is 16,32, or 64 bits, analagous to bitplanes.

@{"BPLCON3" link BPLCON3} contains several bits relating to sprite behavior. SPRES1 and

SPRES0 control sprite resolution, whether they conform to theECS standard

or override tp LORES,HIRES,or SHRES. BRDRSPRT, when high,allows sprites to

be visible in border areas. ESPRM7 thru ESPRM4 allow relocation of the even

sprite color map. OSPRM7 thru OSPRN4 allow relocation of the odd sprite

color map. In the case of attached sprites OSPRM bits are used.

SSCAN2 bit in @{"FMODE" link FMODE} enables sprite scan-doubling. When enabled, individual

SH10 bits in SPRxPOS registers control whether or not a given sprite is to

be scan-doubled. When V0 bit of @{"SPRxPOS" link SPRxPOS} register matches V0 bit of vertical

beam counter, the given sprite`s DMA is allowed to proceed as before. If

the don`t match, then sprite DMA is disabled and LISA reuses the sprite

data

from the previous line. When sprites are scan-doubled, only the position

and control registers need be modified by the programmer; the data

registers need no modification.

NOTE: Sprite vertical start and stop positions must be of the same parity,

i.e. both odd or even.

Compatibility

-------------

RST_pin resets all bits in all registers new to AA. These registers include:

@{"BPLCON3" link BPLCON3}, @{"BPLCON4" link BPLCON4}, @{"CLXCON2" link CLXCON2}, @{"DIWHIGH" link DIWHIGH}, @{"FMODE" link FMODE}.

ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in

BPLCON3 that are never accessed by old copper lists, and in addition are

required by old style copper lists to be in their default

settings.Specifically ECSENA forces the following bits to their default low

settings: BRDRBLNK, BRDNTRAN, ZDCLKEN, EXTBLKEN, and BRDRSPRT.

CLXCON2 is reset by a write to CLXCON, so that old game programs will be

able to correctly detect collisions.

@{"DIWHIGH" link DIWHIGH} is reset by writes to @{"DIWSTRT" link DIWSTRT} or @{"DIWSTOP" link DIWSTRT}. This is interlock is

inhertied from ECS Denise.

Genlock

-------

Lots of new genlock features were added to ECS DENISE and arecarried over

to LISA. ZDBPEN in @{"BPLCON2" link BPLCON2} allows any bitplane, selected by ZDBPSEL2,1,0,to

be used as a transparency mask (ZD pin mirrors contents of selected

bitplane). ZDCTEN disables the old @{"COLOR00" link COLORx} is transparent mode, and allows

the bit31 position of each color in the color table to control

transparency.ZDCLKEN generates a 14MHz clock synchronized with the video

data that can be used by video post-processors. Finally, BRDNTRAN in

@{"BPLCON3" link BPLCON3} generates an opaque border region which can be used to frame live

video.

Color Lookup Table

------------------

The color table has grown from 32 13-bit registers to 256 25-bit registers.

Several new register bits have been added to @{"BPLCON3" link BPLCON3} to facilitate loading

the table with only 32 register addresses. LOCT, selects either the 16 MSB

or LSB for loading. Loading the MSB always loads the LSB as well for

compatibility, so when 24 bit colors are desired load LSB after MSB.

BANK2,1,0 of 8 32 address banks for loading as follows:

+-------+-------+-------+----------------------+

| BANK2 | BANK1 | BANK0 | COLOR ADDRESS RANGE |

+-------+-------+-------+----------------------+

| 0 | 0 | 0 | @{"COLOR00" link COLORx} - COLOR1F |

| 0 | 0 | 1 | COLOR20 - COLOR3F |

| 0 | 1 | 0 | COLOR40 - COLOR5F |

| 0 | 1 | 1 | COLOR60 - COLOR7F |

| 1 | 0 | 0 | COLOR80 - COLOR9F |

| 1 | 0 | 1 | COLORA0 - COLORBF |

| 1 | 1 | 0 | COLORC0 - COLORDF |

| 1 | 1 | 1 | COLORE0 - COLORFF |

+-------+-------+-------+----------------------+

RDRAM bit in @{"BPLCON2" link BPLCON2} causes LISA to interpret all color table accesses as

reads.

Note: There is no longer any need to "scramble" SHRES color table entries.

This artifice is no longer required and pepole who bypass ECS graphics

library calls to do their own 28MHz graphics are to be pointed at and

publicly humiliated.

Collision

---------

A new register @{"CLXCON2" link CLXCON2} contains 4 new bits. ENBP7 and ENBP6 are the enable

bits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MPBP8 are

their match value bits. @{"CLXDAT" link CLXDAT} is unchanged.

Horizontal Comparators

----------------------

All programmable comparators with the exception of @{"VHPOSW" link VHPOSW} have 35nSec

resolution.: @{"DIWHIGH" link DIWHIGH}, @{"HBSTOP" link HBSTOP}, @{"SPRCTL" link SPRCTL}, @{"BPLCON1" link BPLCON1}. BPLCON1 has additional

high-order bits as well. Note that horizontal bit position representing

140nSec resolution has been changed to 3rd least significant bit,where

before it used to be a field`s LSB, For example, bit 00 in BPLCON1 used to

be named PF1H0 and now it`s called PF1H2.

Coercion of 15KHz to 31KHz:

---------------------------

We have added new hardware features to LISA to aid in properly displaying

15KHz and 31KHz viewports together on the same 31KHz display. LISA can

globally set sprite resolution to LORES, HIRES, or SHRES.

LISA will ignore SH10 compare bits in @{"SPRxPOS" link SPRxPOS} when scan-doubling, thereby

allowing ALICE to use these bits individually set scan-doubling.

@endnode

@node registersindex

3. List of registers ordered by address

---------------------------------------

Symbols Used:

& = Register used by DMA channel only.

% = Register used by DMA channel usually, processors sometimes.

+ = Address register pair. Low word uses DB1-DB15, High word DB0-DB4.

~ = Address not writable by the coprocessor unless @{"COPCON" link COPCON} bit 1 is set true

h = new for HiRes chip set.

p = new for IAA chip set.

A = Agnus/Alice chip set.

D = Denise/Lisa chip set.

P = Paula chip.

W = Write.

R = Read.

ER= Early read. This is a DMA transfer to RAM, from either the disk or from

the blitter. Ram timing requires data to be on the bus earlier than

microprocessor read cycles. These transfers are therefore initiated by

Agnus timing, rather than a read address on the register address bus

(RGA).

S = Strobe (Write address with no register bits).

PTL,PTH = 20 bit pointer that addresses DMA data. Must be reloaded by a

processor before use (Vertical blank for bit plane and sprite pointers.

and prior to starting the blitter for blitter pointers). (old chips -

18 bits).

LCL,LCH = 20 bit location (starting address) of DMAdata. Used to

automatically restart pointers. such as the Coprocessor program counter

(during vertical blank), and the audio sample counter (whenever the

audio lentgh count is finished), (Old chips - 18 bits).

MOD = 15 bit Modulo. A number that is automatically added to the memory

address at the end of each line to generate the address for the

beginning of the next line. This allows the blitter (or the display

window) to operate on (or display) a window of data that is smaller

than the actual picture in memory. (memory map) Uses 15 bits, plus

sign extended.

NAME ADDR R/W CHIP(s) FUNCTION

---------------------------------------------------------------------------

@{"BLTDDAT" link BLTDDAT} & ~000 ER A Blitter dest. early read (dummy address)

@{"DMACONR" link DMACON} ~002 R A P Dma control (and blitter status) read

@{"VPOSR" link VPOSR} ~004 R A Read vert most sig. bits (and frame flop

@{"VHPOSR" link VHPOSR} ~006 R A Read vert and horiz position of beam

@{"DSKDATR" link DSKDATR} & ~008 ER P Disk data early read (dummy address)

@{"JOY0DAT" link JOYxDAT} ~00A R D Joystick-mouse 0 data (vert,horiz)

@{"JOT1DAT" link JOYxDAT} ~00C R D Joystick-mouse 1 data (vert,horiz)

@{"CLXDAT" link CLXDAT} ~00E R D Collision data reg. (read and clear)

@{"ADKCONR" link ADKCON} ~010 R P Audio,disk control register read

@{"POT0DAT" link POTxDAT} ~012 R P Pot counter pair 0 data (vert,horiz)

@{"POT1DAT" link POTxDAT} ~014 R P Pot counter pair 1 data (vert,horiz)

@{"POTINP" link POTINP} ~016 R P Pot pin data read

@{"SERDATR" link SERDATR} ~018 R P Serial port data and status read

@{"DSKBYTR" link DSKBYTR} ~01A R P Disk data byte and status read

@{"INTENAR" link INTENA} ~01C R P Interrupt enable bits read

@{"INTREQR" link INTREQ} ~01E R P Interrupt request bits read

@{"DSKPTH" link DSKPTH} + ~020 W A Disk pointer (high 5 bits)

@{"DSKPTL" link DSKPTH} + ~022 W A Disk pointer (low 15 bits)

@{"DSKLEN" link DSKLEN} ~024 W P Disk lentgh

@{"DSKDAT" link DSKDAT} & ~026 W P Disk DMA data write

@{"REFPTR" link REFPTR} & ~028 W A Refresh pointer

@{"VPOSW" link VPOSR} ~02A W A Write vert most sig. bits(and frame flop)

@{"VHPOSW" link VHPOSR} ~02C W A D Write vert and horiz pos of beam

@{"COPCON" link COPCON} ~-2E W A Coprocessor control reg (CDANG)

@{"SERDAT" link SERDAT} ~030 W P Serial port data and stop bits write

@{"SERPER" link SERPER} ~032 W P Serial port period and control

@{"POTGO" link POTGO} ~034 W P Pot count start,pot pin drive enable data

@{"JOYTEST" link JOYTEST} ~036 W D Write to all 4 joystick-mouse counters at

once

@{"STREQU" link STREQU} & ~038 S D Strobe for horiz sync with VB and EQU

@{"STRVBL" link STREQU} & ~03A S D Strobe for horiz sync with VB (vert blank)

@{"STRHOR" link STREQU} & ~03C S D P Strobe for horiz sync

@{"STRLONG" link STREQU} & ~03E S D Strobe for identification of long horiz

line

@{"BLTCON0" link BLTCON0} ~040 W A Blitter control reg 0

@{"BLTCON1" link BLTCON0} ~042 W A Blitter control reg 1

@{"BLTAFWM" link BLTAFWM} ~044 W A Blitter first word mask for source A

@{"BLTALWM" link BLTALWM} ~046 W A Blitter last word mask for source A

@{"BLTCPTH" link BLTxPTH} + ~048 W A Blitter pointer to source C (high 5 bits)

@{"BLTCPTL" link BLTxPTL} + ~04A W A Blitter pointer to source C (low 15 bits)

@{"BLTBPTH" link BLTxPTH} + ~04C W A Blitter pointer to source B (high 5 bits)

@{"BLTBPTL" link BLTxPTL} + ~04E W A Blitter pointer to source B (low 15 bits)

@{"BLTAPTH" link BLTxPTH} + ~050 W A Blitter pointer to source A (high 5 bits)

@{"BLTAPTL" link BLTxPTL} + ~052 W A Blitter pointer to source A (low 15 bits)

@{"BPTDPTH" link BPTxPTH} + ~054 W A Blitter pointer to destn D (high 5 bits)

@{"BLTDPTL" link BLTxPTL} + ~056 W A Blitter pointer to destn D (low 15 bits)

@{"BLTSIZE" link BLTSIZE} ~058 W A Blitter start and size (win/width,height)

@{"BLTCON0L" link BLTCON0} h ~05A W A Blitter control 0 lower 8 bits (minterms)

@{"BLTSIZV" link BLTSIZV} h ~05C W A Blitter V size (for 15 bit vert size)

@{"BLTSIZH" link BLTSIZH} h ~05E W A Blitter H size & start (for 11 bit H size)

@{"BLTCMOD" link BLTxMOD} ~060 W A Blitter modulo for source C

@{"BLTBMOD" link BLTxMOD} ~062 W A Blitter modulo for source B

@{"BLTAMOD" link BLTxMOD} ~064 W A Blitter modulo for source A

@{"BLTDMOD" link BLTxMOD} ~066 W A Blitter modulo for destn D

~068

~06a

~06c

~06e

@{"BLTCDAT" link BLTADAT} & ~070 W A Blitter source C data reg

@{"BLTBDAT" link BLTADAT} & ~072 W A Blitter source B data reg

@{"BLTADAT" link BLTADAT} & ~074 W A Blitter source A data reg

~076

@{"SPRHDAT" link SPRHDAT} &h 078 W A Ext logic UHRES sprite pointer and data

identifier

@{"(BPLHDAT)" link BPLHDAT} ~07A ???? ?????

@{"LISAID" link LISAID} h ~07C R D Chip revision level for Denise/Lisa

@{"DSKSYNC" link DSKSYNC} ~07E W P Disk sync pattern reg for disk read

@{"COP1LCH" link COP1LCH} + 080 W A Coprocessor first location reg

(high 5 bits)

@{"COP1LCL" link COP1LCH} + 082 W A Coprocessor first location reg

(low 15 bits)

@{"COP2LCH" link COP1LCH} + 084 W A Coprocessor second reg

(high 5 bits)

@{"COP2LCL" link COP1LCH} + 086 W A Coprocessor second reg

(low 15 bits)

@{"COPJMP1" link COPJMP1} 088 S A Coprocessor restart at first location

@{"COPJMP2" link COPJMP2} 08A S A Coprocessor restart at second location

@{"COPINS" link COPINS} 08C W A Coprocessor inst fetch identify

@{"DIWSTRT" link DIWSTRT} 08E W A D Display window start

(upper left vert-hor pos)

@{"DIWSTOP" link DIWSTRT} 090 W A D Display window stop

(lower right vert-hor pos)

@{"DDFSTRT" link DDFSTRT} 092 W A Display bit plane data fetch start.hor pos

@{"DDFSTOP" link DDFSTRT} 094 W A Display bit plane data fetch stop.hor pos

@{"DMACON" link DMACON} 096 W A P DMA control write (clear or set)

@{"CLXCON" link CLXCON} 098 W D Collision control

@{"INTENA" link INTENA} 09A W P Interrupt enable bits (clear or set bits)

@{"INTREQ" link INTREQ} 09C W P Interrupt request bits (clear or set bits)

@{"ADKCON" link ADKCON} 09E W P Audio,disk,UART,control

@{"AUD0LCH" link AUDxLCH} + 0A0 W A Audio channel 0 location (high 5 bits)

@{"AUD0LCL" link AUDxLCL} + 0A2 W A Audio channel 0 location (low 15 bits)

@{"AUD0LEN" link AUDxLEN} 0A4 W P Audio channel 0 lentgh

@{"AUD0PER" link AUDxPER} 0A6 W P Audio channel 0 period

@{"AUD0VOL" link AUDxVOL} 0A8 W P Audio channel 0 volume

@{"AUD0DAT" link AUDxDAT} & 0AA W P Audio channel 0 data

0AC

0AE

@{"AUD1LCH" link AUDxLCH} + 0B0 W A Audio channel 1 location (high 5 bits)

@{"AUD1LCL" link AUDxLCL} + 0B2 W A Audio channel 1 location (low 15 bits)

@{"AUD1LEN" link AUDxLEN} 0B4 W P Audio channel 1 lentgh

@{"AUD1PER" link AUDxPER} 0B6 W P Audio channel 1 period

@{"AUD1VOL" link AUDxVOL} 0B8 W P Audio channel 1 volume

@{"AUD1DAT" link AUDxDAT} & 0BA W P Audio channel 1 data

0BC

0BE

@{"AUD2LCH" link AUDxLCH} + 0C0 W A Audio channel 2 location (high 5 bits)

@{"AUD2LCL" link AUDxLCL} + 0C2 W A Audio channel 2 location (low 15 bits)

@{"AUD2LEN" link AUDxLEN} 0C4 W P Audio channel 2 lentgh

@{"AUD2PER" link AUDxPER} 0C6 W P Audio channel 2 period

@{"AUD2VOL" link AUDxVOL} 0C8 W P Audio channel 2 volume

@{"AUD2DAT" link AUDxDAT} & 0CA W P Audio channel 2 data

0CC

0CE

@{"AUD3LCH" link AUDxLCH} + 0D0 W A Audio channel 3 location (high 5 bits)

@{"AUD3LCL" link AUDxLCL} + 0D2 W A Audio channel 3 location (low 15 bits)

@{"AUD3LEN" link AUDxLEN} 0D4 W P Audio channel 3 lentgh

@{"AUD3PER" link AUDxPER} 0D6 W P Audio channel 3 period

@{"AUD3VOL" link AUDxVOL} 0D8 W P Audio channel 3 volume

@{"AUD3DAT" link AUDxDAT} & 0DA W P Audio channel 3 data

0DC

0DE

@{"BPL1PTH" link BPLxPTH} + 0E0 W A Bit plane pointer 1 (high 5 bits)

@{"BPL1PTL" link BPLxPTL} + 0E2 W A Bit plane pointer 1 (low 15 bits)

@{"BPL2PTH" link BPLxPTH} + 0E4 W A Bit plane pointer 2 (high 5 bits)

@{"BPL2PTL" link BPLxPTL} + 0E6 W A Bit plane pointer 2 (low 15 bits)

@{"BPL3PTH" link BPLxPTH} + 0E8 W A Bit plane pointer 3 (high 5 bits)

@{"BPL3PTL" link BPLxPTL} + 0EA W A Bit plane pointer 3 (low 15 bits)

@{"BPL4PTH" link BPLxPTH} + 0EC W A Bit plane pointer 4 (high 5 bits)

@{"BPL4PTL" link BPLxPTL} + 0EE W A Bit plane pointer 4 (low 15 bits)

@{"BPL5PTH" link BPLxPTH} + 0F0 W A Bit plane pointer 5 (high 5 bits)

@{"BPL5PTL" link BPLxPTL} + 0F2 W A Bit plane pointer 5 (low 15 bits)

@{"BPL6PTH" link BPLxPTH} + 0F4 W A Bit plane pointer 6 (high 5 bits)

@{"BPL6PTL" link BPLxPTL} + 0F6 W A Bit plane pointer 6 (low 15 bits)

@{"BPL7PTH" link BPLxPTH} + 0F8 W A Bit plane pointer 7 (high 5 bits)

@{"BPL7PTL" link BPLxPTL} + 0FA W A Bit plane pointer 7 (low 15 bits)

@{"BPL8PTH" link BPLxPTH} + 0FC W A Bit plane pointer 8 (high 5 bits)

@{"BPL8PTL" link BPLxPTL} + 0FE W A Bit plane pointer 8 (low 15 bits)

@{"BPLCON0" link BPLCON0} 100 W A D Bit plane control reg (misc control bits)

@{"BPLCON1" link BPLCON1} 102 W D Bit plane control reg (scroll val PF1,PF2)

@{"BPLCON2" link BPLCON2} 104 W D Bit plane control reg (priority control)

@{"BPLCON3" link BPLCON3} 106 W D Bit plane control reg (enhanced features)

@{"BPL1MOD" link BPLxMOD} 108 W A Bit plane modulo (odd planes,or active-

fetch lines if bitplane scan-doubling is

enabled

@{"BPL2MOD" link BPLxMOD} 10A W A Bit plane modulo (even planes or inactive-

fetch lines if bitplane scan-doubling is

enabled

@{"BPLCON4" link BPLCON4} p 10C W D Bit plane control reg (bitplane and sprite

masks)

@{"CLXCON2" link CLXCON2} p 10e W D Extended collision control reg

@{"BPL1DAT" link BPLxDAT} & 110 W D Bit plane 1 data (parallel to serial con-

vert)

@{"BPL2DAT" link BPLxDAT} & 112 W D Bit plane 2 data (parallel to serial con-

vert)

@{"BPL3DAT" link BPLxDAT} & 114 W D Bit plane 3 data (parallel to serial con-

vert)

@{"BPL4DAT" link BPLxDAT} & 116 W D Bit plane 4 data (parallel to serial con-

vert)

@{"BPL5DAT" link BPLxDAT} & 118 W D Bit plane 5 data (parallel to serial con-

vert)

@{"BPL6DAT" link BPLxDAT} & 11a W D Bit plane 6 data (parallel to serial con-

vert)

@{"BPL7DAT" link BPLxDAT} &p 11c W D Bit plane 7 data (parallel to serial con-

vert)

@{"BPL8DAT" link BPLxDAT} &p 11e W D Bit plane 8 data (parallel to serial con-

vert)

@{"SPR0PTH" link SPRxPTH} + 120 W A Sprite 0 pointer (high 5 bits)

@{"SPR0PTL" link SPRxPTH} + 122 W A Sprite 0 pointer (low 15 bits)

@{"SPR1PTH" link SPRxPTH} + 124 W A Sprite 1 pointer (high 5 bits)

@{"SPR1PTL" link SPRxPTH} + 126 W A Sprite 1 pointer (low 15 bits)

@{"SPR2PTH" link SPRxPTH} + 128 W A Sprite 2 pointer (high 5 bits)

@{"SPR2PTL" link SPRxPTH} + 12A W A Sprite 2 pointer (low 15 bits)

@{"SPR3PTH" link SPRxPTH} + 12C W A Sprite 3 pointer (high 5 bits)

@{"SPR3PTL" link SPRxPTH} + 12E W A Sprite 3 pointer (low 15 bits)

@{"SPR4PTH" link SPRxPTH} + 130 W A Sprite 4 pointer (high 5 bits)

@{"SPR4PTL" link SPRxPTH} + 132 W A Sprite 4 pointer (low 15 bits)

@{"SPR5PTH" link SPRxPTH} + 134 W A Sprite 5 pointer (high 5 bits)

@{"SPR5PTL" link SPRxPTH} + 136 W A Sprite 5 pointer (low 15 bits)

@{"SPR6PTH" link SPRxPTH} + 138 W A Sprite 6 pointer (high 5 bits)

@{"SPR6PTL" link SPRxPTH} + 13A W A Sprite 6 pointer (low 15 bits)

@{"SPR7PTH" link SPRxPTH} + 13C W A Sprite 7 pointer (high 5 bits)

@{"SPR7PTL" link SPRxPTH} + 13E W A Sprite 7 pointer (low 15 bits)

@{"SPR0POS" link SPRxPOS} % 140 W A D Sprite 0 vert-horiz start pos data

@{"SPR0CTL" link SPRxCTL} % 142 W A D Sprite 0 position and control data

@{"SPR0DATA" link SPRxDAT} % 144 W D Sprite 0 image data register A

@{"SPR0DATB" link SPRxDAT} % 146 W D Sprite 0 image data register B

@{"SPR1POS" link SPRxCTL} % 148 W A D Sprite 1 vert-horiz start pos data

@{"SPR1CTL" link SPRxPOS} % 14A W A D Sprite 1 position and control data

@{"SPR1DATA" link SPRxDAT} % 14C W D Sprite 1 image data register A

@{"SPR1DATB" link SPRxDAT} % 14E W D Sprite 1 image data register B

@{"SPR2POS" link SPRxPOS} % 150 W A D Sprite 2 vert-horiz start pos data

@{"SPR2CTL" link SPRxCTL} % 152 W A D Sprite 2 position and control data

@{"SPR2DATA" link SPRxDAT} % 154 W D Sprite 2 image data register A

@{"SPR2DATB" link SPRxDAT} % 156 W D Sprite 2 image data register B

@{"SPR3POS" link SPRxPOS} % 158 W A D Sprite 3 vert-horiz start pos data

@{"SPR3CTL" link SPRxCTL} % 15A W A D Sprite 3 position and control data

@{"SPR3DATA" link SPRxDAT} % 15C W D Sprite 3 image data register A

@{"SPR3DATB" link SPRxDAT} % 15E W D Sprite 3 image data register B

@{"SPR4POS" link SPRxPOS} % 160 W A D Sprite 4 vert-horiz start pos data

@{"SPR4CTL" link SPRxCTL} % 162 W A D Sprite 4 position and control data

@{"SPR4DATA" link SPRxDAT} % 164 W D Sprite 4 image data register A

@{"SPR4DATB" link SPRxDAT} % 166 W D Sprite 4 image data register B

@{"SPR5POS" link SPRxPOS} % 168 W A D Sprite 5 vert-horiz start pos data

@{"SPR5CTL" link SPRxCTL} % 16A W A D Sprite 5 position and control data

@{"SPR5DATA" link SPRxDAT} % 16C W D Sprite 5 image data register A

@{"SPR5DATB" link SPRxDAT} % 16E W D Sprite 5 image data register B

@{"SPR6POS" link SPRxPOS} % 170 W A D Sprite 6 vert-horiz start pos data

@{"SPR6CTL" link SPRxCTL} % 172 W A D Sprite 6 position and control data

@{"SPR6DATA" link SPRxDAT} % 174 W D Sprite 6 image data register A

@{"SPR6DATB" link SPRxDAT} % 176 W D Sprite 6 image data register B

@{"SPR7POS" link SPRxPOS} % 178 W A D Sprite 7 vert-horiz start pos data

@{"SPR7CTL" link SPRxCTL} % 17A W A D Sprite 7 position and control data

@{"SPR7DATA" link SPRxDAT} % 17C W D Sprite 7 image data register A

@{"SPR7DATB" link SPRxDAT} % 17E W D Sprite 7 image data register B

@{"COLOR00" link COLORx} 180 W D Color table 00

@{"COLOR01" link COLORx} 182 W D Color table 01

@{"COLOR02" link COLORx} 184 W D Color table 02

@{"COLOR03" link COLORx} 186 W D Color table 03

@{"COLOR04" link COLORx} 188 W D Color table 04

@{"COLOR05" link COLORx} 18A W D Color table 05

@{"COLOR06" link COLORx} 18C W D Color table 06

@{"COLOR07" link COLORx} 18E W D Color table 07

@{"COLOR08" link COLORx} 190 W D Color table 08

@{"COLOR09" link COLORx} 192 W D Color table 09

@{"COLOR10" link COLORx} 194 W D Color table 10

@{"COLOR11" link COLORx} 196 W D Color table 11

@{"COLOR12" link COLORx} 198 W D Color table 12

@{"COLOR13" link COLORx} 19A W D Color table 13

@{"COLOR14" link COLORx} 19C W D Color table 14

@{"COLOR15" link COLORx} 19E W D Color table 15

@{"COLOR16" link COLORx} 1A0 W D Color table 16

@{"COLOR17" link COLORx} 1A2 W D Color table 17

@{"COLOR18" link COLORx} 1A4 W D Color table 18

@{"COLOR19" link COLORx} 1A6 W D Color table 19

@{"COLOR20" link COLORx} 1A8 W D Color table 20

@{"COLOR21" link COLORx} 1AA W D Color table 21

@{"COLOR22" link COLORx} 1AC W D Color table 22

@{"COLOR23" link COLORx} 1AE W D Color table 23

@{"COLOR24" link COLORx} 1B0 W D Color table 24

@{"COLOR25" link COLORx} 1B2 W D Color table 25

@{"COLOR26" link COLORx} 1B4 W D Color table 26

@{"COLOR27" link COLORx} 1B6 W D Color table 27

@{"COLOR28" link COLORx} 1B8 W D Color table 28

@{"COLOR29" link COLORx} 1BA W D Color table 29

@{"COLOR30" link COLORx} 1BC W D Color table 30

@{"COLOR31" link COLORx} 1BE W D Color table 31

@{"HTOTAL" link HTOTAL} h 1C0 W A Highest number count in horiz line

(VARBEAMEN = 1)

@{"HSSTOP" link HSSTOP} h 1C2 W A Horiz line pos for HSYNC stop

@{"HBSTRT" link HBSTOP} h 1C4 W A D Horiz line pos for HBLANK start

@{"HBSTOP" link HBSTOP} h 1C6 W A D Horiz line pos for HBLANK stop

@{"VTOTAL" link VSSTOP} h 1C8 W A Highest numbered vertical line

(VARBEAMEN = 1)

@{"VSSTOP" link VSSTOP} h 1CA W A Vert line for VBLANK start

@{"VBSTRT" link VBSTOP} h 1CC W A Vert line for VBLANK start

@{"VBSTOP" link VBSTOP} h 1CE W A Vert line for VBLANK stop

@{"SPRHSTRT" link SPRHSTRT} h 1D0 W A UHRES sprite vertical start

@{"SPRHSTOP" link SPRHSTOP} h 1D2 W A UHRES sprite vertical stop

@{"BPLHSTRT" link BPLHSTRT} h 1D4 W A UHRES bit plane vertical stop

@{"BPLHSTOP" link BPLHSTOP} h 1D6 W A UHRES bit plane vertical stop

@{"HHPOSW" link HHPOSR} h 1D8 W A DUAL mode hires H beam counter write

@{"HHPOSR" link HHPOSR} h 1DA R A DUAL mode hires H beam counter read

@{"BEAMCON0" link BEAMCON0} h 1DC W A Beam counter control register

(SHRES,UHRES,PAL)

@{"HSSTRT" link HSSTRT} h 1DE W A Horizontal sync start (VARHSY)

@{"VSSTRT" link HSSTRT} h 1E0 W A Vertical sync start (VARVSY)

@{"HCENTER" link HCENTER} h 1E2 W A Horizontal pos for vsync on interlace

@{"DIWHIGH" link DIWHIGH} h 1E4 W A D Display window upper bits for start/stop

@{"BPLHMOD" link BPLHMOD} h 1E6 W A UHRES bit plane modulo

@{"SPRHPTH" link SPRHPTH} +h 1E8 W A UHRES sprite pointer (high 5 bits)

@{"SPRHPTL" link SPRHPTH} +h 1EA W A UHRES sprite pointer (low 15 bits)

@{"BPLHPTH" link BPLHPTH} +h 1EC W A VRam (UHRES) bitplane pointer (hi 5 bits)

@{"BPLHPTL" link BPLHPTH} +h 1EE W A VRam (UHRES) bitplane pointer (lo 15 bits)

RESERVED 1F0 - 1FA

@{"FMODE" link FMODE} p 1FC W A D Fetch mode register

NO-OP(NULL) 1FE Can also indicate last 2 or 3 refresh

cycles or the restart of the COPPER after

lockup.

@endnode

@node moreregisters "Some Notes to Start Width"

4. List of Registers Ordered Alphabetically

-------------------------------------------

P = New register in Pandora chip set

p = Stuff added or changed in hires chips

H = New register in hires chips

h = stuff added or changed in hires chips

A = Agnus/Alice chip

D = Denise/Lisa chip

P = Paula chip

W = Write

R = Read

ER = Early read. This is a DMA data transfer to RAM, from either the disk

or from the blitter, Ram timing requires data to be on the bus

earlier than microprocessor read cycles. These transfers are

therefore initiated by Agnus timing, rather than a read address on

the register address bus (RGA).

@endnode

@node ADKCON ADKCON

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

ADKCON 09E W P Audio,Disk,Uart,Control write

ADKCONR 010 R P Audio,Disk,Uart,Control read

+-------+-------------+-------------------------------------------+

| BITS | USE | DESCRIPTION |

+-------+-------------+-------------------------------------------+

| 15 | SET/CLEAR | Set/clear control bit.determines if bits |

| | | written with a 1 get set or cleared.bits |

| | | written with a zero are always unchanged. |

| | | |

| | | +------+---------------+ |

| 14-13 | PRECOMP 1-0 | | CODE | PRECOMP VALUE | |

| | | +------+---------------+ |

| | | | 00 | none | |

| | | | 01 | 140 ns | |

| | | | 10 | 280 ns | |

| | | | 11 | 560 ns | |

| | | +------+---------------+ |

| | | |

| 12 | MFMPREC | (1 = MFM precomp / 0 = GCR precomp) |

| 11 | UARTBRK | Forces a UART break (clears TXD) if true |

| 10 | WORDSYNC | Enables disk read synchronizing on a word |

| | | equal to DISK SYNC CODE, Located in |

| | | address @{"DSKSYNC" link DSKSYNC} (7E). |

| 09 | MSBSYNC | Enables disk read synchrinizing on the |

| | | MSB (most signif bit) appl type GCR |

| 08 | FAST | Disk data clock rate control 1=fast(2us) |

| | | 0=slow(4us) |

| | | (Fast for MFM or 2us,slow for 4us GCR) |

| 07 | USE3PN | Use audio channel 3 to modulate nothing |

| 06 | USE2P3 | Use audio channel 2 to modulate period |

| | | of channel 3 |

| 05 | USE1P2 | Use audio channel 1 to modulate period |

| | | of channel 2 |

| 04 | USE0P1 | Use audio channel 0 to modulate period |

| | | of channel 1 |

| 03 | USE3VN | Use audio channel 3 to modulate nothing |

| | | |

| 02 | USE2V3 | Use audio channel 2 to modulate volume |

| | | of channel 3 |

| 01 | USE1V2 | Use audio channel 1 to modulate volume |

| | | of channel 2 |

| 00 | USE0V1 | Use audio channel 0 to modulate volume |

| | | of channel 1 |

+-------+-------------+-------------------------------------------+

Note: If both period and volume aremodulated on the same channel,

the period and volume will be alternated. First @{"AUDxDAT" link AUDxDAT} word

is used for V6-V0 of @{"AUDxVOL" link AUDxVOL}. Second AUDxDAT word is used for

P15-P0 of @{"AUDxPER" link AUDxPER}. This alternating sequence is repeated.

@endnode

@node AUDxLCH AUDxLCH

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

AUDxLCH h 0A0 W A Audio channel x location (high 5 bits)

(old-3 bits)

@endnode

@node AUDxLCL AUDxLCL

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

AUDxLCL 0A2 W A Audio channel x location (low 15 bits)

This pair of registers contains the 20 bit starting

address(location) of audio channel x (x=0,1,2,3)DMA

data. This is not a pointer reg and therfore only

needs to be reloaded if a diffrent memory location

is to be outputted.

@endnode

@node AUDxLEN AUDxLEN

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

AUDxLEN 0A4 W P Audio channel x length

This reg contains the lentgh (number of words) of

audio channel x DMA data.

@endnode

@node AUDxPER AUDxPER

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

AUDxPER h 0A6 W P Audio channel x period

This reg contains the period (rate) of audio channel

x DMA data transfer.

The minimum period is 124 clocks. This means that

the smallest number that should be placed in this

reg is 124.

@endnode

@node AUDxVOL AUDxVOL

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

AUDxVOL 0A8 W P Audio channel x volume

This reg contains the volume setting for audio channel x.

Bits 6,5,4,3,2,1,0 specify 65 linear volume levels as shown below.

+--------+--------------------------------------------------+

| BITS | USE |

+--------+--------------------------------------------------+

| -15-07 | Not used |

| 06 | Forces volume to max (64 ones,no zeros) |

| 05-00 | Sets one of the 64 levels (000000 = no output, |

| | 111111 = 63 ones, one zero) |

+--------+--------------------------------------------------+

@endnode

@node AUDxDAT AUDxDAT

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

AUDxDAT 0AA W P Audio channel x data

This reg is the audio channel x (x=0,1,2,3) DMA

data buffer. It contains 2 bytes of data (each

byte is a twos complement signed integer) that

are outputed sequentially (with digital to analog

conversion)to the audio output pins. With maximum

volume, each byte can drive the audio outputs

with 0.8 volts(peak to peak,typ). The audio DMA

channel controller automatically transfers data

to this reg from RAM. The processor can also

write directly to this reg. When the DMA data is

finished (words outputted=lentgh)and the data in

this reg has been used, an audio channel interrupt

request is set.

@endnode

@node BEAMCON0 BEAMCON0

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BEAMCON0 h 1DC W A Beam counter control bits

+-------+----------------------------+

| BIT# | FUNCTION |

+-------+----------------------------+

| 15 | (unused) |

| 14 | HARDDIS |

| 13 | LPENDIS |

| 12 | VARVBEN |

| 11 | LOLDIS |

| 10 | CSCBEN |

| 9 | VARVSYEN |

| 8 | VARHSYEN |

| 7 | VARBEAMEN |

| 6 | DUAL |

| 5 | PAL |

| 4 | VARCSYEN |

| 3 | (unused, formerly BLANKEN) |

| 2 | CSYTRUE |

| 1 | VSYTRUE |

| 0 | HSYTRUE |

+-------+----------------------------+

HARDDIS = This bit is used to disable the hardwire vertical horizontal

window limits. It is cleared upon reset.

LPENDIS = When this bit is a low and LPE (@{"BPLCON0" link BPLCON0},BIT 3) is enabled, the

light-pen latched value(beam hit position) will be read by

@{"VHPOSR" link VHPOSR}, @{"VPOSR" link VPOSR} and @{"HHPOSR" link HHPOSR}. When

the bit is a high the light-pen latched value is ignored and

the actual beam counter position is read by VHPOSR, VPOSR, and

HHPOSR.

VARVBEN = Use the comparator generated vertical blank (from @{"VBSTRT" link VBSTOP}, @{"VBSTOP" link VBSTOP})

to run the internal chip stuff-sending RGA signals to Denise,

starting sprites,resetting light pen. It also disables the hard

stop on the vertical display window.

LOLDIS = Disable long line/short toggle. This is useful for DUAL mode

where even multiples are wanted, or in any single display

where this toggling is not desired.

CSCBEN = The variable composite sync comes out on the HSY pin, and the

variable conosite blank comes out on the VSY pin. The idea is

to allow all the information to come out of the chip for a

DUAL mode display. The normal monitor uses the normal composite

sync, and the variable composite sync &blank come out the HSY &

VSY pins. The bits VARVSTEN & VARHSYEN (below) have priority over

this control bit.

VARVSYEN= Comparator VSY -> VSY pin. The variable VSY is set vertically on

@{"VSSTRT" link HSSTRT}, reset vertically on @{"VSSTOP" link VSSTOP}, with the horizontal position

for set set & reset @{"HSSTRT" link HSSTRT} on short fields (all fields are short

if LACE = 0) and @{"HCENTER" link HCENTER} on long fields (every other field if

LACE = 1).

VARHSYEN= Comparator HSY -> HSY pin. Set on HSSTRT value, reset on @{"HSSTOP" link HSSTOP}

value.

VARBEAMEN=Enables the variable beam counter comparators to operate

(allowing diffrent beam counter total values) on the main horiz

counter. It also disables hard display stops on both horizontal

and vertical.

DUAL = Run the horizontal comparators with the alternate horizontal beam

counter, and starts the UHRES pointer chain with the reset of

this counter rather than the normal one. This allows the UHRES

pointers to come out more than once in a horizontal line,

assuming there is some memory bandwidth left (it doesn`t work in

640*400*4 interlace mode) also, to keep the two displays synced,

the horizontal line lentghs should be multiples of each other.

If you are amazingly clever, you might not need to do this.

PAL = Set appropriate decodes (in normal mode) for PAL. In variable

beam counter mode this bit disables the long line/short line

toggle- ends up short line.

VARCSYEN= Enables CSY from the variable decoders to come out the CSY

(VARCSY is set on @{"HSSTRT" link HSSTRT} match always, and also on @{"HCENTER" link HCENTER}

match when in vertical sync. It is reset on @{"HSSTOP" link HSSTOP} match when VSY

and on both @{"HBSTRT" link HBSTOP} & @{"HBSTOP" link HBSTOP} matches during VSY. A reasonable

composite can be generated by setting HCENTER half a horiz line

from @{"HSSTRT" link HSSTRT}, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER, with

HBSTRT at (HSSTOP-HSSTRT) before HSSTRT.

HSYTRUE, VSYTRUE, CSYTRUE = These change the polarity of the

HSY*, VSY*, & CSY* pins to HSY, VSY, & CSY respectively for

input & output.

@endnode

@node BLTxPTH BLTxPTH

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTxPTH h 050 W A Blitter Point to x (High 5 bits)

See also: @{"BLTxPTL" link BLTxPTL}

@endnode

@node BLTxPTL BLTxPTL

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTxPTL h 052 W A Blitter Pointer to x (Low 15 bits)

This pair of registers (see also: @{"BLTxPTH" link BLTxPTH})

contains the 20 bit address of Blitter source (X=A,B,C) or dest.

(x=D) DMA data. This pointer must be preloaded with the

starting address of the data to be processed by the blitter. After

the Blitter is finished it will contain the last data address

(plus increment and modulo).

@endnode

@node BLTxMOD BLTxMOD

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTxMOD 064 W A Blitter Modulo x

This register contains the Modulo for Blitter source (x=A,B,C)

or Dest (X=D). A Modulo is a number that is automatically

added to the address at the end of each line, in order that

the address then points to the start of the next line. Each

source or destination has it's own Modulo, allowing each

to be a different size, while an identical area of each is

used in the Blitter operation.

@endnode

@node BLTAFWM BLTAFWM

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTAFWM 044 W A Blitter first word mask for source A

See also: @{"BLTALWM" link BLTALWM}

@endnode

@node BLTALWM BLTALWM

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTALWM 046 W A Blitter last word mask for source A

The patterns in these two registers (see also: @{"BLTAFWM" link BLTAFWM})

are "anded" with the first and last words of each line of data

from Source A into the Blitter. A zero in any bit overrides

data from Source A. These registers should be set to all

"ones" for fill mode or for line drawing mode.

@endnode

@node BLTxDAT BLTxDAT

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTxDAT 074 W A Blitter source x data reg.

This register holds Source x (x=A,B,C) data for use by the Blitter.

It is normally loaded by the Blitter DMA channel, however it

may also be preloaded by the microprocessor.

@endnode

@node BLTDDAT BLTDDAT

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTDDAT 000 W A Blitter destination data register

This register holds the data resulting from each word of

Blitter operation until it is sent to a RAM destination.

This is a dummy address and cannot be read by the micro.

The transfer is automatic during Blitter operation.

@endnode

@node BLTSIZE BLTSIZE

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTSIZE 058 W A Blitter start and size (win/width, height)

This register contains the width and height of the blitter operation

(in line mode width must = 2, height = line length). Writing

to this register will start the Blitter, and should be done last,

after all pointers and control registers have been initialized.

BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00

H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 W5 W4 W3 W2 W1 W0

H=Height=Vertical lines (10 bits=1024 lines max)

W=Width=Horiz pixels (6 bits=64 words=1024 pixels max)

@endnode

@node BLTCON0 BLTCON0

NAME rev ADDR type chip Description

---------------------------------------------------------------------------

BLTCON0 040 W A Blitter control register 0

BLTCON0L H 05A W A Blitter control register 0 (lower 8 bits)

This is to speed up software - the upper bits are

often the same.

BLTCON1 h 042 W A Blitter control register 1

These two control registers are used together to control blitter

operations. There are 2 basic modes, are and line, which are

selected by bit 0 of BLTCON1, as show below.

+--------------------------+---------------------------+

| AREA MODE ("normal") | LINE MODE (line draw) |

+------+---------+---------+------+---------+----------+

| BIT# | BLTCON0 | BLTCON1 | BIT# | BLTCON0 | BLTCON1 |

+------+---------+---------+------+---------+----------+

| 15 | ASH3 | BSH3 | 15 | ASH3 | BSH3 |

| 14 | ASH2 | BSH2 | 14 | ASH2 | BSH2 |

| 13 | ASH1 | BSH1 | 13 | ASH1 | BSH1 |

| 12 | ASA0 | BSH0 | 12 | ASH0 | BSH0 |

| 11 | USEA | 0 | 11 | 1 | 0 |

| 10 | USEB | 0 | 10 | 0 | 0 |

| 09 | USEC | 0 | 09 | 1 | 0 |

| 08 | USED | 0 | 08 | 1 | 0 |

| 07 | LF7 | DOFF | 07 | LF7 | DPFF |

| 06 | LF6 | 0 | 06 | LF6 | SIGN |

| 05 | LF5 | 0 | 05 | LF5 | OVF |

| 04 | LF4 | EFE | 04 | LF4 | SUD |

| 03 | LF3 | IFE | 03 | LF3 | SUL |

| 02 | LF2 | FCI | 02 | LF2 | AUL |

| 01 | LF1 | DESC | 01 | LF1 | SING |

| 00 | LF0 | LINE(=0)| 00 | LF0 | LINE(=1) |

+------+---------+---------+------+---------+----------+

ASH3-0 Shift value of A source

BSH3-0 Shift value of B source and line texture

USEA Mode control bit to use source A

USEB Mode control bit to use source B

USEC Mode control bit to use source C

USED Mode control bit to use destination D

LF7-0 Logic function minterm select lines

EFE Exclusive fill enable

IFE Inclusive fill enable

FCI Fill carry input

DESC Descending (dec address)control bit

LINE Line mode control bit

SIGN Line draw sign flag

OVF Line/draw r/l word overflow flag

SUD Line draw, Sometimes up or down (=AUD)