This diff is a first pass for a somewhat generic FPGA driver and server which
allows other tasks in the system to manage actions such as loading bitstreams.
In addition the server task exposes a register interface abstraction for a SPI
peripheral running as part of the bitstream application.

These two combined interfaces if you will, allow a process such as a sequencer
to manage both the device and interact with application logic through a single
entry point.

The driver is generic enough that in addition to the ECP5 implementation found
in this diff, we can support the iCE40 and possibly future devices.

The intend is for the FPGA server to not use a separate SPI driver if not required
reduce system resources by absorbing the functionality needed to handle the
SPI peripheral. This work requires some refactoring to expose more of the SPI
server functionality as a library and this will be done in a follow-up.

Note that the ECP5 driver is split into a top and bottom implementation.
Currently only one bottom implementation is provided, but a second (involving
transparent use of a SPI mux and GPIO extend) is in the works.

Finally, Hiffy/Humility support for interacting with an FPGA will be provided in
a follow up diff.