Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag #282
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rosethompson
commented
Apr 26, 2023
rosethompson
commented
- Started putting together the arty a7 board package files.
- Finally building ddr3 xilinx ip from script.
- Added more support for Arty A7 board.
- Fixed syntax errors in arty7 top level.
- Updates for arty a7.
- Fixed sum bugs with arty a7 ila script.
- Updated to help debut Jacob's crossbar woes.
- Fixed more bugs in the ila debug constraints.
- Progress on arty a7 board.
- Finally fixed the ddr3 mig script to work correclty.
- Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
- Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
- Fixed more issues with arty a7 constarints.
- OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
- Finally got the arty a7 to build.
- Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
- Adding in the ILA to the arty a7.
- Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.
- Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way.
- Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8.
- Found the DDR3 memory is not ready when issuing the first store.
- Fixed timing constraint issue.
- Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
- It's almost working.
- Added more signals to debugger in hopes I can figure out why the mig is not responding.
- More debug stuff.
- Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed.
- Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram. but the data is wrong.
- Yeah We boot linux on the arty a7!
- Updated fpga Makefile to work with both the Arty and VCU platforms.
- FPGA makefile update.
- Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data.
… than the ddr4 mig. Go figure.
…he arty a7 board. mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
… the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
…ide works. However the CPU is stuck in reset. Not really sure what's going on there.
…I wish they'd named it that way.
… out of reset, but we are stuck at PCM = 10b8.
…age is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
…is not responding.
…ause the polarity was reversed.
…d to dram. but the data is wrong.
…reds of gigabytes of data.
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