bugfix: allow unsetting variables in configuration files #593
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Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>
Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>
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Misc. Enhancements/Bugfixes
VERILOG_POWER_DEFINEas an optional variable.Steps
Yosys.JsonHeader,Verilator.Lint,Odb.WriteVerilogHeaderVERILOG_POWER_DEFINE.