[docs] Update naming explanation for newer firtool #3454
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Firtool improvements have optimized many examples to the point where they do not show anything. Using registers and assigning the same value to multiple outputs helps make the examples show interesting naming behavior.
jackkoenig
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Aug 3, 2023
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| In the following example, we prefix additional logic with "ECO", where `Example4` is pre-ECO and `Example5` is post-ECO: | ||
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| ```scala mdoc | ||
| class Example4 extends Module { | ||
| val in = IO(Input(UInt(2.W))) | ||
| val out = IO(Output(UInt())) | ||
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| val add = in + in + in | ||
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| out := add + 1.U | ||
| } | ||
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| class Example5 extends Module { | ||
| val in = IO(Input(UInt(2.W))) | ||
| val out = IO(Output(UInt())) | ||
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| val add = in + in + in | ||
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| out := prefix("ECO") { add + 1.U + in } | ||
| } | ||
| ``` | ||
| ```scala mdoc:verilog | ||
| emitSystemVerilog(new Example4) | ||
| emitSystemVerilog(new Example5) | ||
| ``` |
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I deleted the ECO example only because I literally cannot figure out a reliable way to make temporaries show up in the Verilog (other than naming the signals myself but that sort of defeats the purpose).
I do think we should have an ECO example but we need to make sure it captures enough complexity to actually be interesting. I'm also worried that firtool's much more aggressive optimizations will make this sort of ECO stuff harder to do so it may just not really be showable at the moment (without adding some sort of optimization barrier primitive).
If anyone can come up with a good example, I'm happy to add it back.
mikeurbach
approved these changes
Aug 3, 2023
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Firtool improvements have optimized many examples to the point where they do not show anything. Using registers and assigning the same value to multiple outputs helps make the examples show interesting naming behavior.
h/t @lsteveol for noticing and pointing this out on Gitter
Here's the rendered markdown after running mdoc: https://gist.github.com/jackkoenig/907017545186407f1353d145f48a4cdf
Compare this to what's currently on the website: https://www.chisel-lang.org/chisel3/docs/explanations/naming.html
Contributor Checklist
docs/src?Type of Improvement
Desired Merge Strategy
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3.5.x,3.6.x, or5.xdepending on impact, API modification or big change:6.0)?Enable auto-merge (squash), clean up the commit message, and label withPlease Merge.Create a merge commit.