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Add support for fmsub and fnmsub instructions on x86 #8888

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merged 7 commits into from
Jul 13, 2024

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UnlimitedHummus
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Issue #8602

Allows generating fmsub and fnmsub instructions as mentioned in the issue.

@UnlimitedHummus UnlimitedHummus requested a review from a team as a code owner June 30, 2024 21:14
@UnlimitedHummus UnlimitedHummus requested review from fitzgen and removed request for a team June 30, 2024 21:14
@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator cranelift:area:x64 Issues related to x64 codegen labels Jun 30, 2024
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Thanks! Overall looks good to me, modulo the one comment below.

Can you also add some run tests in addition to the compile tests, to make sure that the runtime behavior is as-expected as well? Since FMA is not quite the same across architectures, it may make sense to put these run tests under cranelift/filetests/filetests/isa/x64 as well.

cranelift/codegen/src/isa/x64/lower.isle Show resolved Hide resolved
@UnlimitedHummus
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Sure, I'll add the runtime tests later, when I have time.

@afonso360
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We already have some run tests that run on all arch's here (1, 2, 3). None of them test load sinking, so that would be a nice addition.

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This LGTM! I double checked the new instruction encodings against the intel manual and they all check out. Thanks!

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To add runtime tests for load sinking, I would just duplicate some existing testcases and add loads to them. This doesn't test that the load is actually sunk, but rather that the results are still correct with load sinking. Is that the intention? Or am I missing some different type of testcase I could write?

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fitzgen commented Jul 2, 2024

That is a good thing to test, but generally I was just asking for runtests that check that the new lowerings that turn multiple clif instructions into a single machine instruction produce the same values that interpreting the individual clif instructions would.

See for example

https://github.com/bytecodealliance/wasmtime/blob/main/cranelift/filetests/filetests/runtests/iabs.clif#L1-L18

although we only care about the interpreter and x86-64 here.

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Is this what you had in mind? I didn't find a better way to test this, other than to store the value on the stack and then load it from there again.

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If that's good I will add some more tests of course.

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Yeah! Just something to ensure that the instruction gets emitted and runs properly. I wouldn't worry about trying to get all of the variations running, that might be too much (In my opinion).

; popq %rbp
; retq

;; negate first, then load
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This could generate more efficient core by selecting vfnmsub132ss instead and skipping the negation.

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I added some tests, but also identified an optimization I missed. This only affects the case where the negation happens before the load. I think the order of the two shouldn't matter. I still need to look into how to write rules to handle that case.

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I added some tests, but also identified an optimization I missed. This only affects the case where the negation happens before the load. I think the order of the two shouldn't matter. I still need to look into how to write rules to handle that case.

This PR is already a nice improvement even if it doesn't optimize every case, so: If you want to dig into that you're welcome to, but I'd also be happy to merge this as-is. If you decide not to fix it right now, then it would be great to open a new issue describing what's not working, and include a link to that issue in the comments on the test that illustrates the problem.

That said, this is failing in CI right now. The error looks weird to me and I'm not sure whether you just need to re-run CRANELIFT_TEST_BLESS=1 cargo test -p cranelift-tools --test filetests or if there's something stranger going on, so please let us know if you have any trouble.

@UnlimitedHummus
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CI failing was due to me annotating a copy of the expected output. I moved my comment before the testcase, which fixed that. I tried adding some rules to improve code generation for this case yesterday, but that didn't work. So I'd have to take a closer look at ISLE to see why it doesn't generate the right code. Not sure when I'll get around to that so I opened an issue describing the missed optimization like you suggested.

@afonso360 afonso360 added this pull request to the merge queue Jul 13, 2024
Merged via the queue into bytecodealliance:main with commit 225d20e Jul 13, 2024
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4 participants