This folder contains a collection of files related to various experiments performed in the Digital Logic & Microprocessor Architecture course. These experiments cover different aspects of digital circuit design, simulation, and implementation using FPGA hardware. Below is a breakdown of the files and their contents, organized by experiment number.

• Experiment_1.qsf: Quartus settings file that defines the project settings and configuration for the experiment.
• Experiment_1.qws: Quartus workspace file that organizes all the project files for Experiment 1.
• Experiment_1.v: Verilog file containing the design and logic for Experiment 1.
• Experiment_1.v.bak: Backup of the Verilog file in case of changes or errors.

• experiment2.qsf: Quartus settings file for Experiment 2.
• experiment2.qws: Quartus workspace file for Experiment 2.
• experiment2.v: Verilog file for Experiment 2, containing the design logic.
• experiment2.v.bak: Backup version of the Verilog file.

• experiment3.qsf: Quartus settings file for Experiment 3.
• experiment3.qws: Quartus workspace file for Experiment 3.
• experiment3.v: Verilog file with the logic and design of Experiment 3.
• experiment3.v.bak: Backup version of the Verilog file.

• experiment4.qsf: Quartus settings file for Experiment 4.
• experiment4.qws: Quartus workspace file for Experiment 4.
• experiment4.v: Verilog file with the logic for implementing sequential logic in Experiment 4.
• experiment4.v.bak: Backup version of the Verilog file.

• experiment5.qsf: Quartus settings file for Experiment 5.
• experiment5.v: Verilog file for the design logic of Experiment 5.
• mem.mif: Memory Initialization File (MIF) that defines the memory contents used in Experiment 5.
• memory.txt: Text file containing memory data used in Experiment 5.
• ramport.qip: Quartus IP file for the RAM module used in Experiment 5.
• ramport.v: Verilog code for the RAM module in Experiment 5.
• ramport_bb.v: Testbench file for simulating the RAM module in Experiment 5.

• experiment6.qsf: Quartus settings file for Experiment 6.
• experiment6.qws: Quartus workspace file for Experiment 6.
• experiment6.v: Verilog file with the logic for Experiment 6.
• experiment6.v.bak: Backup version of the Verilog file.

• ascii.mif.txt: Memory initialization file for ASCII characters.
• bcd.v: Verilog file for Binary Coded Decimal (BCD) conversion in Experiment 7.
• exp7.v: Verilog file containing the main design for Experiment 7.
• exp7.vt: Testbench file for simulating Experiment 7.
• keyboard.v: Verilog file for simulating the keyboard interface.
• ps2_keyboard.v: Verilog code for handling the PS/2 keyboard interface.
• scancode_ram.v: Verilog code for handling scancode data from the keyboard.

• experiment8_2.qsf: Quartus settings file for Experiment 8.
• experiment8_2.v: Verilog code for implementing the VGA display logic.
• experiment8_2.v.bak: Backup version of the Verilog file for Experiment 8.
• picture.mif: Memory initialization file with picture data for the VGA display.
• picture.mif.bak: Backup of the memory initialization file.
• ram_memory.v: Verilog code for the RAM module used in Experiment 8.
• vga_ctrl.v: Verilog code for controlling the VGA output.

• dot_ram.v: Verilog file for implementing dot-based RAM for display.
• experiment9.v.bak: Backup version of the Verilog file for Experiment 9.
• function_clock.v: Verilog code for generating clock signals for Experiment 9.
• vga_font.txt: Text file containing the font data used in the VGA display.
• vga_gen.v: Verilog code for generating the VGA signal.

These files represent the design, simulation, and implementation of various digital logic circuits and systems used throughout the course. From basic combinational circuits to advanced CPU design, memory hierarchy, and VGA display systems, each experiment file plays a critical role in understanding digital circuit design and microprocessor architecture.

These files should be organized within their respective directories to ensure the project structure remains clear and manageable. The use of Verilog for hardware description and Quartus for synthesis and simulation is integral to developing a strong foundation in digital logic.