cpu/stm32/periph/adc: fix setting ADC clock #19629
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The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability.
Enoch247
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19268: shell_lock: don't set CONFIG_SHELL_SHUTDOWN_ON_EXIT r=benpicco a=benpicco 19629: cpu/stm32/periph/adc: fix setting ADC clock r=benpicco a=Enoch247 ### Contribution description The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU. ### Testing procedure I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random [STM32F1](https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) and [STM32F2](https://www.st.com/resource/en/reference_manual/rm0033-stm32f205xx-stm32f207xx-stm32f215xx-and-stm32f217xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), and they are clocked similar to the F7 I have. ### Issues/PRs references None known. 19670: cpu/stm32: stm32f4 BRR from BSRR r=benpicco a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 Co-authored-by: Benjamin Valentin <benpicco@beuth-hochschule.de> Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com> Co-authored-by: Joshua DeWeese <jdeweese@primecontrols.com> Co-authored-by: Karl Fessel <karl.fessel@ovgu.de>
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19629: cpu/stm32/periph/adc: fix setting ADC clock r=benpicco a=Enoch247 ### Contribution description The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU. ### Testing procedure I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random [STM32F1](https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) and [STM32F2](https://www.st.com/resource/en/reference_manual/rm0033-stm32f205xx-stm32f207xx-stm32f215xx-and-stm32f217xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), and they are clocked similar to the F7 I have. ### Issues/PRs references None known. 19670: cpu/stm32: stm32f4 BRR from BSRR r=benpicco a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 Co-authored-by: Joshua DeWeese <jdeweese@primecontrols.com> Co-authored-by: Karl Fessel <karl.fessel@ovgu.de>
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Contribution description
The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability.
I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU.
Testing procedure
I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random STM32F1 and STM32F2, and they are clocked similar to the F7 I have.
Issues/PRs references
None known.