boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board #19170

gschorcht · 2023-01-18T13:31:17Z

Contribution description

This PR add the support for the Sipeed Longan Nano board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from boards/seeedstudio-gd32 to boards/common/gd32v.

[Update] At first glance, the existing peripheral definition for seeedstudio-gd32 seems to fit exactly for sipeed-longan-nano. But at second glance it becomes clear that seeedstudio-gd32 which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards.

This PR depends on PR #19166 and includes this PR for the moment.

Testing procedure

t.b.d.

Issues/PRs references

Depends on PR #19166

riot-ci · 2023-01-18T15:05:40Z

Murdock results

✔️ PASSED

42ec4f0 tests: add sipeed-longan-nano to Makefile.ci

Success	Failures	Total	Runtime
6796	0	6796	08m:58s

Artifacts

Documentation preview

aabadie · 2023-01-19T07:17:36Z

Needs rebase and static tests are failing because of missing inline doxygen comment (maybe update the exclude pattern for doxygen ?)

gschorcht · 2023-01-19T07:37:56Z

Needs rebase and static tests are failing because of missing inline doxygen comment (maybe update the exclude pattern for doxygen ?)

I have it already rebased locally. At the moment I'm wondering whether it makes sense to move back the peripheral configuration for timers and UARTs back from common to the board definitions. The boards differ too much.

benpicco · 2023-01-19T12:25:19Z

I'm wondering whether it makes sense to move back the peripheral configuration for timers and UARTs back from common to the board definitions.

Yes please!
This also makes it easier to create new boards.
If peripherals can be mapped to arbitrary pins, a common config does not make much sense.

gschorcht · 2023-01-19T13:04:01Z

If peripherals can be mapped to arbitrary pins, a common config does not make much sense.

Another approach could be to define the most common peripheral configuration in periph_common_conf which is included at the end of board's periph_conf.f and to use something like HAVE_UART_CONFIG and HAVE_TIMER_CONFIG conditionals to indicate that the board defines its own configuration. For example, both boards use same SPI peripheral configuration. What do you think about this approach?

benpicco · 2023-01-19T13:09:01Z

That's how it's done for STM32, which I think is pretty similar to this family 😉

gschorcht · 2023-01-19T13:27:06Z

That's how it's done for STM32

Ah, sodaq* is a good example. So it seems to be better to define a bunch of cfg_*_default.h files that are included by the board or an own configuration is defined for that peripheral?

which I think is pretty similar to this family

Yes, the GD32VF103 is (almost) exactly the same as the STM32F103, but unfortunately with its own identifiers. So the peripheral drivers are actually just modified copies of the STM32F1 drivers.

gschorcht · 2023-01-19T13:51:29Z

static tests are failing because of missing inline doxygen comment (maybe update the exclude pattern for doxygen ?)

Would it make sense to add common peripheral configuration identifiers like uart_config, UART_NUMOF, ... that are defined for each board to generic_exclude_patterns instead of adding them to exclude_patterns for each board again and again?

benpicco · 2023-01-19T16:13:36Z

boards/common/gd32v/include/cfg_timer_default.h

+#if defined(GD32VF103C8) || defined(GD32VF103CB) || \
+    defined(GD32VF103R8) || defined(GD32VF103RB) || \
+    defined(GD32VF103T8) || defined(GD32VF103TB) || \
+    defined(GD32VF103V8) || defined(GD32VF103VB)


Could we check for RCU_APB1EN_TIMER3EN_Msk/RCU_APB1EN_TIMER4EN_Msk instead?

Unfortunatly not since there are no separate definitions for the MCU models. That is RCU_APB1EN_TIMER3EN_Msk/RCU_APB1EN_TIMER4EN_Msk are always defined even if the MCU doesn't support.

Ooops, there are no such definitions. I should test variable CPU_MODEL or define these identifiers as macros.

benpicco · 2023-01-23T01:13:17Z

boards/common/gd32v/include/board_common.h

+#define XTIMER_HZ                   MHZ(1)
+#define XTIMER_WIDTH                (16)


Is this even still used by anything?

I was not sure. Since a large number of boards still define it and the seeedstudio-gd32 board definition used it, I decided to keep it. I can remove to see what happens.

Uh sorry, turns out I was wrong about this.
This is still needed.

Really, where? I removed it and Murdock was happy and nightlies down't give errors.

Video.mp4

This doesn't look like 1s intervals to me 😅

Which test application is it?

examples/blinky, see #19205

gschorcht · 2023-01-23T10:52:50Z

I had to rebase to resolve the conflicts.

bors · 2023-01-23T22:31:51Z

Already running a review

benpicco · 2023-01-23T22:34:54Z

bors cancel

bors merge

bors · 2023-01-23T22:34:56Z

Canceled.

benpicco · 2023-01-23T22:35:18Z

bors merge

bors · 2023-01-23T22:35:20Z

Already running a review

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-01-23T22:41:29Z

Build failed (retrying...):

Murdock

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-01-23T23:08:43Z

Build failed:

Murdock

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

benpicco · 2023-01-24T11:09:50Z

bors merge

bors · 2023-01-24T14:38:21Z

Build succeeded:

19185: cpu/gd32v: add periph_gpio_irq support r=gschorcht a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=gschorcht a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

19188: cpu/gd32v: add periph_adc support r=gschorcht a=gschorcht ### Contribution description This PR provides the `periph_adc` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. This PR depends on PR #19170 and includes this PR to be compilable since includes the ADC configuration also for Sipeed Longan Nano board. ### Testing procedure `tests/periph_adc` should work on any GD32VF103 board. ### Issues/PRs references Depends on PR #19170 Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

19055: shell/gnrc_icmpv6_echo: acquire ZTIMER_USEC clock for time measurement r=benpicco a=jue89 19188: cpu/gd32v: add periph_adc support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_adc` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. This PR depends on PR #19170 and includes this PR to be compilable since includes the ADC configuration also for Sipeed Longan Nano board. ### Testing procedure `tests/periph_adc` should work on any GD32VF103 board. ### Issues/PRs references Depends on PR #19170 19225: sys/net/dhcpv6: include IA Prefix Option in SOLICIT r=benpicco a=benpicco Co-authored-by: Jue <me@jue.yt> Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>

gschorcht requested review from leandrolanzieri, jia200x and MrKevinWeiss as code owners January 18, 2023 13:31

github-actions bot added Area: boards Area: Board ports Area: cpu Area: CPU/MCU ports Area: doc Area: Documentation Area: Kconfig Area: Kconfig integration labels Jan 18, 2023

gschorcht force-pushed the boards/sipeed-longan-nano branch from 41fe5ec to 49c95f4 Compare January 18, 2023 13:33

github-actions bot removed the Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms label Jan 18, 2023

gschorcht added the State: WIP State: The PR is still work-in-progress and its code is not in its final presentable form yet label Jan 19, 2023

gschorcht force-pushed the boards/sipeed-longan-nano branch from 49c95f4 to a0fece0 Compare January 19, 2023 15:49

github-actions bot added the Area: tools Area: Supplementary tools label Jan 19, 2023

gschorcht force-pushed the boards/sipeed-longan-nano branch from a0fece0 to d617852 Compare January 19, 2023 16:01

benpicco added CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR and removed CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Jan 19, 2023

gschorcht removed the State: WIP State: The PR is still work-in-progress and its code is not in its final presentable form yet label Jan 22, 2023

gschorcht mentioned this pull request Jan 22, 2023

cpu/gd32v: add periph_adc support #19188

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gschorcht added 2 commits January 24, 2023 00:39

examples: add sipeed-longan-nano to Makefile.ci

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tests: add sipeed-longan-nano to Makefile.ci

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gschorcht requested review from miri64, smlng, aabadie, MichelRottleuthner and fjmolinas as code owners January 23, 2023 23:40

github-actions bot added Area: examples Area: Example Applications Area: tests Area: tests and testing framework labels Jan 23, 2023

bors bot merged commit d1072c2 into RIOT-OS:master Jan 24, 2023

gschorcht deleted the boards/sipeed-longan-nano branch February 4, 2023 12:17

MrKevinWeiss added this to the Release 2023.04 milestone Apr 25, 2023

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boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board #19170

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boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board #19170

boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board #19170

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