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cpu/efm32/timer_series2: fix interaction with pm_layered #18814
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Murdock results✔️ PASSED 54e915e cpu/efm32/timer_series2: sync STATUS register
ArtifactsThis only reflects a subset of all builds from https://ci-prod.riot-os.org. Please refer to https://ci.riot-os.org for a complete build for now. |
The timer hasn't been enabled yet, if the STATUS isn't RUNNING, yet ...
Make sure the STATUS register has been synced between the different clock domains. Especially the LETIMER needs some time to update the STATUS register after it has been enabled. If the LETIMER is started and stopped with just a short delay, pm_layered gets confused because the timer seems to be inactive ...
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@gschorcht Thank you for reviewing! Does your ACK still apply? I've refactored the methods |
The testing example above still works with the refactored version of this PR. |
@gschorcht may I ask you for a quick look, if your ACK still applies? |
Sorry for the delay, I was quite busy by other tasks the last days. The ACK still applies, the last change is semantically the same. |
Thank you for reviewing! :-) |
Contribution description
While working on #17607, I found two bugs in the
periph_timer
implementation for Gecko Series 2 EFM32 CPUs:During
timer_start()
andtimer_stop()
, the driver checks whether the timer isn't running yet resp. is currently running. Power modes are just blocked and unblocked in those cases to prevent leaks iftimer_start()
ortimer_stop()
is called multiple times in a row.timer_start()
had the wrong logic.pm_block()
wasn't called.timer_stop()
has to make sure that the STATUS register is up-to-date.Testing procedure
Abusing
examples/hello-world
with #17607 in place:Diff for hello-world
Issues/PRs references