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cpu/sam0_common: UART: implement inverted RX & TX #14300

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merged 1 commit into from
Jun 17, 2020
Merged

cpu/sam0_common: UART: implement inverted RX & TX #14300

merged 1 commit into from
Jun 17, 2020

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benpicco
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The UART TX and TX lines on SAMD5x and SAML1x can be inverted.
However, the flags don't do exactly what one would expect.

See errata 2.18.5: SERCOM-UART: TXINV and RXINV Bits Reference:

The TXINV and RXINV bits in the CTRLA register have inverted functionality.

Workaround:
In software interpret the TXINV bit as a functionality of RXINV, and conversely,
interpret the RXINV bit as a functionality of TXINV.

Testing procedure

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@benpicco benpicco added Type: new feature The issue requests / The PR implemements a new feature for RIOT Area: cpu Area: CPU/MCU ports labels Jun 16, 2020
@benpicco
cpu/sam0_common: UART: implement inverted RX & TX
585dc15 
The UART TX and TX lines on SAMD5x and SAML1x can be inverted.
However, the flags don't do exactly what one would expect.

See errata 2.18.5: SERCOM-UART: TXINV and RXINV Bits Reference:

> The TXINV and RXINV bits in the CTRLA register have inverted functionality.
>
> Workaround:
> In software interpret the TXINV bit as a functionality of RXINV, and conversely,
> interpret the RXINV bit as a functionality of TXINV.
@benpicco benpicco force-pushed the cpu/sam0_common/uart_txinv branch from 0c0569e to 585dc15 Compare June 16, 2020 20:55
@benpicco benpicco added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label Jun 16, 2020
fjmolinas
fjmolinas approved these changes Jun 17, 2020
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I don't have a BOARD supporting this functionality, but implementation matches the datasheet and errata. ACK.

@fjmolinas fjmolinas merged commit 4c05c02 into RIOT-OS:master Jun 17, 2020
@benpicco benpicco deleted the cpu/sam0_common/uart_txinv branch June 17, 2020 09:44
@miri64 miri64 added this to the Release 2020.07 milestone Jun 24, 2020
@benpicco benpicco mentioned this pull request Oct 11, 2020
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@benpicco benpicco mentioned this pull request Nov 24, 2023
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@fjmolinas fjmolinas fjmolinas approved these changes

@dylad dylad Awaiting requested review from dylad dylad is a code owner

@keestux keestux Awaiting requested review from keestux keestux is a code owner

@MrKevinWeiss MrKevinWeiss Awaiting requested review from MrKevinWeiss

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Area: cpu Area: CPU/MCU ports CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Type: new feature The issue requests / The PR implemements a new feature for RIOT
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@benpicco @fjmolinas @miri64