Fully functional SpaceWire router. Implemented in VHDL and under continuous development. See manual. Repository also contains a UART-SpaceWire adapter and several implementation files including constraints for Xilinx FPGAs.

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

MCom-02 SpaceWire SWIC controller tools