opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V CPU Core (RV32IM)

A self-hosting and educational C optimizing compiler

32-bit Superscalar RISC-V CPU

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

RISC-V 32-bit microcontroller developed in Verilog

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Small Processing Unit 32: A compact RV32I CPU written in Verilog

RISC-V Nox core

RISC-V RV32I[MA] emulator with ELF support

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

A Single Cycle Risc-V 32 bit CPU

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

An open-source 32-bit RISC-V soft-core processor

伴伴學 RISC-V RV32I Architecture CPU

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

RISCV CPU implementation in SystemVerilog