Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

This project demonstrates DSP capabilities of Terasic DE2-115

Matrix multiplication on multiple Nios II cores

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

High Dynamic Range imaging with Altera DE2-115.

FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.

DE2简易电子计时器，使用VHDL语言开发，在DE2-115开发板上测试运行通过。该电子计时器具有四种工作模式：正常计时、从外部设置当前的小时数、从外部设置当前的分钟数、从外部设置当前的秒数，同时具有可逆的计时功能。

Simple LED blink example for DE2-115

Дипломная работа специалиста за 2015 год на тему "Акустическая система мониторинга на основе пространственной фильтрации звуковых сигналов".

A complete hardware description of a non-pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA.

EDA技术与应用，DE2实验，DE2-115开发板实验，包含了实验1-4。

Design for board DE2-115, microprocessor soft running a uCOS-II(Real Time Operating System). Application to test is a Lift program

This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)

FPGA_TETRIS

RV32IM System-on-Chip (SoC)

6位简易处理器的硬件设计，使用VHDL语言开发，在DE2-115开发板上运行通过。

HDLMake template for terasIC DE2-115

a ping-pong-game by fpga developboard de2-115

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).