cpu-design

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Here are 43 public repositories matching this topic...

phoeniX-Digital-Design / phoeniX

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RISC-V Embedded Processor for Approximate Computing

cpu fpga embedded-systems riscv microprocessor computer-architecture vlsi risc-v approximate-computing cpu-design

Updated Nov 2, 2024
Verilog

mrmcsoftware / CPUsimulator

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This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.

javascript html emulator simulator assembler assembly-language logisim cpu-simulator cpu-design computer-simulator logisim-cpu logisim-evolution

Updated Oct 1, 2023
HTML

SimonBuxx / Linkuit-Studio

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A platform for learning and experimenting with logic circuits

simulator simulation logic logic-gates logic-circuit-simulator logic-circuit logic-simulator cpu-design logic-simulation logiccircuit

Updated Mar 29, 2024
C++

rauhul / ece411

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Computer Architecture UIUC SP 2018

cache lc3 branch-prediction cpu-design

Updated May 4, 2018
Assembly

sarthi92 / vector_processor

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Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

memory verilog cpu-design vector-processor

Updated Nov 29, 2018
Verilog

arsalanjabbari / RISCV-CPU-Design

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In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

risc-v multicycle-processor cpu-design

Updated Aug 14, 2023
Verilog

martandrMC / cpu-design

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This repository contains files regarding my CPU designs

java verilog assembly-language systemverilog cpu-design

Updated Dec 30, 2023
Verilog

sarthi92 / cpu_cisc

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Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme

verilog cpu-design

Updated May 4, 2018
Verilog

FISC-Project / FISC-SystemVerilog

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FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

c arm cpu cpp verilog systemverilog computer-architecture cpu-design

Updated Aug 22, 2019
Verilog

ArvinDelavari / Digital-Circuits-Verilog

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Sample Verilog codes for digital circuits

cpu vscode verilog computer-architecture hdl risc-v iverilog digital-design hardware-description-language cpu-design digital-design-and-computer-organization

Updated Oct 22, 2023
Verilog

EmreKumas / Processor_Design

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This is an implementation of a simple CPU in Logisim and Verilog.

cpu instructions assembler alu logisim modelsim control-unit cpu-design cpu-simulation register-file data-memory address-memory

Updated Jan 11, 2019
Verilog

emmapaczkowski / ELEC374

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The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

risc-processor cpu-design

Updated Apr 10, 2021
Verilog

arsalanjabbari / MIPS-CPU-Design

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This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

mips cpu-design single-cycle-processor