Adds missing ARM target ABI information (BinaryAnalysisPlatform#1386)

* Update LLVM backend to work with version 12 This may also work with later versions, but I did not test them * Updates the ARM target with ABI information according to AACPS * Runs `make indent` Co-authored-by: bmourad01 <bqm0621@ocsdev02.ocsportal.draper.com>
thestr4ng3r · Dec 9, 2021 · beea850 · beea850
1 parent c93fb75
commit beea850
Showing 1 changed file with 35 additions and 0 deletions.
diff --git a/lib/arm/arm_target.ml b/lib/arm/arm_target.ml
@@ -53,6 +53,33 @@ let status_regs = Theory.Role.Register.[
     [overflow_flag], regs Arm_env.[vf];
   ]
 
+(* AACPS, §5.1.1 Core registers:
+
+   - The first four registers r0-r3 (a1-a4) are used to pass
+     argument values into a subroutine and to return a result
+     value from a function. They may also be used to hold intermediate
+     values within a routine (but, in general, only between subroutine
+     calls).
+
+   - Register r12 (IP) may be used by a linker as a scratch register
+     between a routine and any subroutine it calls (for details,
+     see §5.3.1.1, Use of IP by the linker). It can also be used within
+     a routine to hold intermediate values between subroutine calls.
+
+   - The role of register r9 is platform specific. A virtual platform
+     may assign any role to this register and must document this usage.
+     For example, it may designate it as the static base (SB) in a
+     position-independent data model, or it may designate it as the thread
+     register (TR) in an environment with thread-local storage. The usage
+     of this register may require that the value held is persistent across
+     all calls. A virtual platform that has no need for such a special
+     register may designate r9 as an additional callee-saved variable
+     register, v6.
+
+   - A subroutine must preserve the contents of the registers
+     r4-r8, r10, r11 and SP (and r9 in PCS variants that designate
+     r9 as v6).
+*)
 let regs32 = Theory.Role.Register.[
     [general; integer], regs Arm_env.[
         r0; r1; r2; r3; r4; r5; r6; r7; r8; r9; r10; r11; r12;
@@ -64,6 +91,14 @@ let regs32 = Theory.Role.Register.[
     [thumb], regs Arm_env.[
         r0; r1; r2; r3; r4; r5; r6; r7; sp; lr;
       ];
+    [function_argument], regs Arm_env.[r0; r1; r2; r3];
+    [function_return], regs Arm_env.[r0; r1];
+    [caller_saved], regs Arm_env.[
+        r0; r1; r2; r3; r12; lr;
+      ];
+    [callee_saved], regs Arm_env.[
+        r4; r5; r6; r7; r8; r9; r10; r11; sp;
+      ];
   ] @ status_regs
 
 let vfp2regs = Theory.Role.Register.[