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ptl: Add FPGA overlay configuration
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Add PTL configuration changes required to build FW
for FPGA. After next SOF rebase default target will be
build for RVP, so for FPGA we will use configuration
overlay.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
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jxstelter authored and pjdobrowolski committed Jun 19, 2024
1 parent ff3e5dc commit 24bda01
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3 changes: 3 additions & 0 deletions app/overlays/ptl/fpga_overlay.conf
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
CONFIG_DAI_DMIC_HW_IOCLK=19200000

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