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ustcpetergu: Added COD code
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petergu committed Jan 18, 2021
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16 changes: 16 additions & 0 deletions 计算机组成原理/codes/ustcpetergu/README.md
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### 2020 年春季学期 COD 实验报告 & 代码

原项目/历史记录请见 https://github.com/ustcpetergu/USTC-COD-Labs/

- Lab1: ALU & sort
- Lab2: Regfile & RAM & FIFO
- Lab3: Single cycle CPU
- Lab4: Multiple cycle CPU
- Lab5: 5-stage pipeline CPU
- Lab6: CPU & UART on ebaz4205 (testing video in report.md)

Rebuild projects from TCL(for example):

```
vivado -mode batch -source lab6.tcl -tclargs --project_name lab6
```
276 changes: 276 additions & 0 deletions 计算机组成原理/codes/ustcpetergu/ip/alu/component.xml
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67 changes: 67 additions & 0 deletions 计算机组成原理/codes/ustcpetergu/ip/alu/src/alu.v
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`timescale 1ns / 1ps
// ALU
// 2020 COD Lab1
// ustcpetergu

module alu
#(parameter WIDTH = 32)
(
input [2:0]m, // selection
input [WIDTH-1:0]a, b, // input
output [WIDTH-1:0]y, // result
output zf, // zero flag
output cf, // carry out flag: WIDTH bit
output of // overflow flag: WIDTH-1 sign bit
);

reg [WIDTH-1:0]regy;
reg regcf;
reg regof;
reg regzf;
assign y = regy;
assign cf = regcf;
assign of = regof;
assign zf = regzf;
// assign zf = (regy == 0);

always @ (a, b, m) begin
case(m)
3'b000: begin // add
{regcf, regy} = a + b;
regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) |
(a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]);
regzf = (regy == 0);
end
3'b001: begin // sub
{regcf, regy} = a - b;
regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) |
(a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]);
regzf = (regy == 0);
end
3'b010: begin // and
regy = a & b;
regzf = (regy == 0);
regcf = 0;
regof = 0;
end
3'b011: begin // or
regy = a | b;
regzf = (regy == 0);
regcf = 0;
regof = 0;
end
3'b100: begin // xor
regy = a ^ b;
regzf = (regy == 0);
regcf = 0;
regof = 0;
end
default: begin // error
regy = 0;
regzf = 0;
regcf = 0;
regof = 0;
end
endcase
end
endmodule
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